diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index ae12279..8718928 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -619,6 +619,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 
 phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 {
+	printf("debug point 1\n");
+	mdelay(2000);
 	unsigned int i, first_ctrl, last_ctrl;
 #ifdef CONFIG_PPC
 	unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
@@ -628,7 +630,8 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 
 	first_ctrl = pinfo->first_ctrl;
 	last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
-
+	printf("debug point 2\n");
+	mdelay(2000);
 	/* Compute it once normally. */
 #ifdef CONFIG_FSL_DDR_INTERACTIVE
 	if (tstc() && (getc() == 'd')) {	/* we got a key press of 'd' */
@@ -651,7 +654,8 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 	default:
 		break;
 	}
-
+	printf("debug point 3\n");
+	mdelay(2000);
 	/*
 	 * Program configuration registers.
 	 * JEDEC specs requires clocks to be stable before deasserting reset
@@ -682,6 +686,8 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 		fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
 					deassert_reset ? 1 : 0);
 	}
+	printf("debug point 4\n");
+	mdelay(2000);
 	if (deassert_reset) {
 		/* Use board FPGA or GPIO to deassert reset signal */
 		if (pinfo->board_mem_de_reset) {
@@ -696,7 +702,8 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 						i, 2);
 		}
 	}
-
+	printf("debug point 5\n");
+	mdelay(2000);
 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
 	fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
 #endif
@@ -773,8 +780,10 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 		}
 	}
 #endif
+	printf("debug point 6\n");
+	mdelay(2000);
 
-	debug("total_memory by %s = %llu\n", __func__, total_memory);
+	printf("total_memory by %s = %llu\n", __func__, total_memory);
 
 #if !defined(CONFIG_PHYS_64BIT)
 	/* Check for 4G or more.  Bad. */
@@ -787,7 +796,8 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 		total_memory = CONFIG_MAX_MEM_MAPPED;
 	}
 #endif
-
+	printf("debug point 7\n");
+	mdelay(2000);
 	return total_memory;
 }
 
@@ -813,7 +823,7 @@ phys_size_t fsl_ddr_sdram(void)
 	info.board_mem_de_reset = board_deassert_mem_reset;
 	remove_unused_controllers(&info);
 
-	return 0;//__fsl_ddr_sdram(&info);
+	return __fsl_ddr_sdram(&info);
 }
 
 #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS