diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 3ca9fc1..ef08489 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -451,7 +451,7 @@ phys_size_t initdram(int board_type)
 	/*
 	 * Initialize and enable DDR ECC.
 	 */
-	//ddr_enable_ecc(dram_size);
+	ddr_enable_ecc(dram_size);
 #endif
 
 #if defined(CONFIG_FSL_LBC)
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index fcfe693..588e1bd 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -14,6 +14,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
+	printf("dram init before (fsp)\n");
+	mdelay(2000);
+
 	phys_size_t ram_size = 0;
 	const struct hob_header *hdr;
 	struct hob_res_desc *res_desc;
@@ -37,7 +40,9 @@ int dram_init(void)
 	gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list,
 					       &gd->arch.mrc_output_len);
 #endif
-
+	
+	printf("dram init after\n");
+	mdelay(2000);
 	return 0;
 }
 
diff --git a/common/board_f.c b/common/board_f.c
index c0fb5f1..a1f6156 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -188,9 +188,11 @@ static int init_func_ram(void)
 #else
 	int board_type = 0;	/* use dummy arg */
 #endif
-
+	printf("Before init func ram\n");
+	mdelay(2000);
 	gd->ram_size = initdram(board_type);
-
+	printf("after init func ram\n");
+	mdelay(2000);
 	if (gd->ram_size > 0)
 		return 0;
 
@@ -705,9 +707,12 @@ static int setup_board_extra(void)
 #ifdef CONFIG_POST
 static int init_post(void)
 {
+	printf("init post\n");
+	mdelay(2000);
 	post_bootmode_init();
 	post_run(NULL, POST_ROM | post_bootmode_get(0));
-
+	printf("init post end\n");
+	mdelay(2000);
 	return 0;
 }
 #endif
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index f9f840b..a365152 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -758,8 +758,6 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const common_timing_params_t *common_dimm)
 {
-	printf("DRAM cfg\n");
-	mdelay(5000);
 	unsigned int mem_en = 0;		/* DDR SDRAM interface logic enable */
 	unsigned int sren;		/* Self refresh enable (during sleep) */
 	unsigned int ecc_en;		/* ECC enable. */
@@ -846,8 +844,6 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 }
 
 static void set_ddr_sdram_cfg_mem_en(fsl_ddr_cfg_regs_t *ddr){
-	printf("Mem enable\n");
-	mdelay(5000);
 	int mem_en = 1;
 	ddr->ddr_sdram_cfg = ( ddr->ddr_sdram_cfg
 			| ((mem_en & 0x1) << 31));
@@ -860,8 +856,6 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 			       const memctl_options_t *popts,
 			       const unsigned int unq_mrs_en)
 {
-	printf("DRAM cfg2\n");
-	mdelay(5000);
 	unsigned int frc_sr = 0;	/* Force self refresh */
 	unsigned int sr_ie = 0;		/* Self-refresh interrupt enable */
 	unsigned int odt_cfg = 0;	/* ODT configuration */
diff --git a/post/post.c b/post/post.c
index 4194edb..5717f9c 100644
--- a/post/post.c
+++ b/post/post.c
@@ -27,6 +27,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int post_init_f(void)
 {
+	printf("post_init_f start\n");
+	mdelay(20000;
 	int res = 0;
 	unsigned int i;
 
@@ -40,7 +42,7 @@ int post_init_f(void)
 	gd->post_init_f_time = post_time_ms(0);
 	if (!gd->post_init_f_time)
 		printf("%s: post_time_ms not implemented\n", __FILE__);
-
+	printf("post_init_f end\n");
 	return res;
 }