diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index ef08489..3ca9fc1 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -451,7 +451,7 @@ phys_size_t initdram(int board_type)
 	/*
 	 * Initialize and enable DDR ECC.
 	 */
-	ddr_enable_ecc(dram_size);
+	//ddr_enable_ecc(dram_size);
 #endif
 
 #if defined(CONFIG_FSL_LBC)
diff --git a/common/board_f.c b/common/board_f.c
index bc42718..c0fb5f1 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -953,9 +953,9 @@ static init_fnc_t init_sequence_f[] = {
 #endif
 	INIT_FUNC_WATCHDOG_RESET
 #if defined(CONFIG_SYS_DRAM_TEST)
-	//testdram,
+	testdram,
 #endif /* CONFIG_SYS_DRAM_TEST */
-	//INIT_FUNC_WATCHDOG_RESET
+	INIT_FUNC_WATCHDOG_RESET
 
 #ifdef CONFIG_POST
 	init_post,
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 586c899..36542f5 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -781,7 +781,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 	sren = popts->self_refresh_in_sleep;
 	if (common_dimm->all_dimms_ecc_capable) {
 		/* Allow setting of ECC only if all DIMMs are ECC. */
-		ecc_en = popts->ecc_mode;
+		ecc_en = 0;//popts->ecc_mode;
 	} else {
 		ecc_en = 0;
 	}
@@ -910,7 +910,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 
 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/* Use the DDR controller to auto initialize memory. */
-	d_init = popts->ecc_init_using_memctl;
+	d_init = 0;//popts->ecc_init_using_memctl;
 	ddr->ddr_data_init = 0x22221111;//CONFIG_MEM_INIT_VALUE;
 	debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 #else