From b69f4109f6a8b581a10c141e0f9b2193df109db6 Mon Sep 17 00:00:00 2001
From: Jason <jason.dejesus@uconn.edu>
Date: Thu, 16 Jan 2020 15:08:52 -0500
Subject: [PATCH] setting mem init later

---
 cmd/USB_build.c             | 23 +++++++++++++++++++++++
 drivers/ddr/fsl/ctrl_regs.c | 27 +++++++++++++++++----------
 2 files changed, 40 insertions(+), 10 deletions(-)
 create mode 100644 cmd/USB_build.c

diff --git a/cmd/USB_build.c b/cmd/USB_build.c
new file mode 100644
index 0000000..fe368bc
--- /dev/null
+++ b/cmd/USB_build.c
@@ -0,0 +1,23 @@
+/*
+ * USB Build script
+ */
+#include <common.h>
+#include <command.h>
+#include <flash.h>
+#include <fat.h>
+#include <usb.h>
+
+//usb start
+static int do_build(void){
+	printf("starting USB...\n");
+	do_usb_start();
+
+//fatls usb 0:1 (dont need)
+//fatload usb 0:1 1000000 u-boot-nor.bin
+
+//protect off 0xEBF40000 +$filesize
+//erase 0xEBF40000 +$filesize
+//cp.b 1000000 0xEBF40000 $filesize
+//protect on 0xEBF40000 +$filesize
+return 0;
+}
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index a9b4291..1f986ae 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -777,14 +777,14 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int mem_halt = 0;	/* memory controller halt */
 	unsigned int bi = 0;		/* Bypass initialization */
 
-	mem_en = 1;
+	//mem_en = 1;
 	sren = popts->self_refresh_in_sleep;
-	if (common_dimm->all_dimms_ecc_capable) {
+	//if (common_dimm->all_dimms_ecc_capable) {
 		/* Allow setting of ECC only if all DIMMs are ECC. */
 		//ecc_en = popts->ecc_mode;
-	} else {
+	//} else {
 		//ecc_en = 0;
-	}
+	//}
 
 	if (common_dimm->all_dimms_registered &&
 	    !common_dimm->all_dimms_unbuffered)	{
@@ -843,6 +843,12 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 	debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 }
 
+static void set_ddr_sdram_cfg_mem_en(fsl_ddr_cfg_regs_t *ddr){
+	int mem_en = 1;
+	ddr->ddr_sdram_cfg = ( ddr->ddr_sdram_cfg
+			| ((mem_en & 0x1) << 31))
+}
+
 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 			       fsl_ddr_cfg_regs_t *ddr,
@@ -908,16 +914,16 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 
 	x4_en = popts->x4_en ? 1 : 0;
 
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+//#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/* Use the DDR controller to auto initialize memory. */
 	//d_init = popts->ecc_init_using_memctl;
-	ddr->ddr_data_init = 0x22221111;//CONFIG_MEM_INIT_VALUE;
-	debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
-#else
+	//ddr->ddr_data_init = 0x22221111;//CONFIG_MEM_INIT_VALUE;
+	//debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
+//#else
 	/* Memory will be initialized via DMA, or not at all. */
 	//d_init = 0;
-#endif
-
+//#endif
+	
 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 	md_en = popts->mirrored_dimm;
 #endif
@@ -2485,6 +2491,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
 		ddr->debug[18] = popts->cswl_override;
 
 	set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
+	set_ddr_sdram_cfg_mem_en(ddr);
 	set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
 			   cas_latency, additive_latency, unq_mrs_en);
 	set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);