diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index f3a623d..e2464dd 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -760,7 +760,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 {
 	unsigned int mem_en;		/* DDR SDRAM interface logic enable */
 	unsigned int sren;		/* Self refresh enable (during sleep) */
-	unsigned int ecc_en = 0;		/* ECC enable. */
+	unsigned int ecc_en;		/* ECC enable. */
 	unsigned int rd_en;		/* Registered DIMM enable */
 	unsigned int sdram_type;	/* Type of SDRAM */
 	unsigned int dyn_pwr;		/* Dynamic power management mode */
@@ -779,13 +779,13 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 
 	//mem_en = 1;
 	sren = popts->self_refresh_in_sleep;
-	//if (common_dimm->all_dimms_ecc_capable) {
+	if (common_dimm->all_dimms_ecc_capable) {
 		/* Allow setting of ECC only if all DIMMs are ECC. */
-		//ecc_en = popts->ecc_mode;
-	//} else {
-		//ecc_en = 0;
-	//}
-
+		ecc_en = popts->ecc_mode;
+	} else {
+		ecc_en = 0;
+	}
+	ecc_en = 0;
 	if (common_dimm->all_dimms_registered &&
 	    !common_dimm->all_dimms_unbuffered)	{
 		rd_en = 1;
@@ -818,7 +818,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 	hse = popts->half_strength_driver_enable;
 
 	/* set when ddr bus width < 64 */
-	//acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
+	acc_ecc_en = 0;//(dbw != 0 && ecc_en == 1) ? 1 : 0;
 
 	ddr->ddr_sdram_cfg = (0
 			| ((mem_en & 0x1) << 31)
@@ -840,13 +840,14 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 			| ((mem_halt & 0x1) << 1)
 			| ((bi & 0x1) << 0)
 			);
-	debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
+	printf("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 }
 
 static void set_ddr_sdram_cfg_mem_en(fsl_ddr_cfg_regs_t *ddr){
 	int mem_en = 1;
 	ddr->ddr_sdram_cfg = ( ddr->ddr_sdram_cfg
 			| ((mem_en & 0x1) << 31));
+printf("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 }
 
 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
@@ -863,7 +864,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 	unsigned int x4_en = 0;		/* x4 DRAM enable */
 	unsigned int obc_cfg;		/* On-The-Fly Burst Chop Cfg */
 	unsigned int ap_en;		/* Address Parity Enable */
-	unsigned int d_init = 0;		/* DRAM data initialization */
+	unsigned int d_init;		/* DRAM data initialization */
 	unsigned int rcw_en = 0;	/* Register Control Word Enable */
 	unsigned int md_en = 0;		/* Mirrored DIMM Enable */
 	unsigned int qd_en = 0;		/* quad-rank DIMM Enable */
@@ -914,19 +915,20 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 
 	x4_en = popts->x4_en ? 1 : 0;
 
-//#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/* Use the DDR controller to auto initialize memory. */
-	//d_init = popts->ecc_init_using_memctl;
-	//ddr->ddr_data_init = 0x22221111;//CONFIG_MEM_INIT_VALUE;
-	//debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
-//#else
+	d_init = popts->ecc_init_using_memctl;
+	ddr->ddr_data_init = 0x22221111;//CONFIG_MEM_INIT_VALUE;
+	debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
+#else
 	/* Memory will be initialized via DMA, or not at all. */
-	//d_init = 0;
-//#endif
+	d_init = 0;
+#endif
 	
 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 	md_en = popts->mirrored_dimm;
 #endif
+	d_init = 0;
 	qd_en = popts->quad_rank_present ? 1 : 0;
 	ddr->ddr_sdram_cfg_2 = (0
 		| ((frc_sr & 0x1) << 31)
@@ -947,7 +949,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 		| ((rcw_en & 0x1) << 2)
 		| ((md_en & 0x1) << 0)
 		);
-	debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
+	printf("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 }
 
 #ifdef CONFIG_SYS_FSL_DDR4