Programming Assignment 1: Non-pipelined riscv-uconn Simulator
A non-pipelined CPU simulator for the RISC-V riscv-uconn instruction set architecture. The simulator translates machine code created by the riscv-uconn assembler, and executes instructions one at a time. Each instruction goes through a Fetch, Decode, Execute, Memory, and Writeback stage of processing.
Build Instructions
$ make
Unit Tests
Several unit tests are provided in the unittests directory. These unit tests must be assembled
before use with the simulator. Ensure that the assembler is compiled (this should be done after completing PA0).
The unit tests can all be assembled by executing the following command:
$ ../assembler/assembler unittests/unit_test_file.asm <path>/unit_test_file.out
where unit_test_file is any of the unit test files (written in riscv-uconn assembly) in the
unittests directory. You may also use the provided `assemble_all.sh' script:
$ bash assemble_all.sh
Usage
$ ./simulator <path>/unit_test_file.out
where unit_test_file.out may be any assembled program file generated by the riscv-uconn
assembler.