sim_stages.c

/**
 * University of Connecticut
 * CSE 4302/ CSE 5302 / ECE 5402: Computer Architecture
 * Fall 2023
 * TODO: Your Name Here
 * 
 * Programming Assignment 1: Non-pipelined Simulator
 * 
 * riscy-uconn: sim_stages.c
 * 
 */

#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "instruction_map.h"
#include "sim_core.h"
#include "sim_stages.h"

/**
 * Debug flags
 */
bool debug = false;        // Set to 1 for additional debugging information.
bool pipe_trace = true;    // Set to 1 for pipe trace.
int pipe_trace_mode = 3;   // Set the pipe trace mode (see the PA1 documentation for more info)

/**
 * Fetch stage implementation.
 * DO NOT MODIFY.
 */

struct State fetch(void) {
    
    //A new initialized state structure
    struct State fetch_out = {0};
    
    //Use the current PC to store i) The instruction ii) The instruction's address
    fetch_out.inst = memory[pc / 4];
    fetch_out.inst_addr = pc;

    //Advance the program counter and return the state structure
    advance_pc(4);
    return fetch_out;
}

/**
 * Decode stage implementation
 */
struct State decode(struct State fetch_out) {

    /**
     * TODO: Your code for the decode stage here.
    */
    
    return fetch_out;    

}

/**
 * Execute stage implementation
 */
struct State execute(struct State decode_out) {

    /**
     * TODO: Your code for the execute stage here.
    */
    
    return decode_out;
}

/**
 * Memory stage implementation
 */
struct State memory_stage(struct State ex_out) {
    
    /**
     * TODO: Your code for the memory stage here.
    */

    return ex_out;
}


/**
 * Writeback stage implementation
 */
unsigned int writeback(struct State mem_out) {

    /**
     * TODO: Your code for the writeback stage here.
    */
    
    return mem_out.inst;
}

/**
 * Advance PC.
 * DO NOT MODIFY.
 */
void advance_pc(int step) {
    pc_n = pc + step;
}