README.md

# Programming Assignment 2: Pipelined riscy-uconn Simulator

A 5-stage pipelined CPU simulator for the MIPS-like riscy-uconn instruction set architecture. The
simulator translates machine code created by the riscy-uconn assembler, and executes instructions
one at a time. Each instruction goes through a Fetch, Decode, Execute, Memory and Writeback stage of
processing.

## Build Instructions
    $ make

## Usage
    $ ./simulator assembled_program_file.out FORWARDING_ENABLED

where `assembled_program_file.out` may be any assembled program file generated by the riscy-uconn
assembler, and `FORWARDING_ENABLED` may be 0 (disabled) or 1 (enabled).

## Unit Tests
Several unit tests are provided in the `unittests` directory. These unit tests must be assembled
before use with the simulator by executing the following command:

    $ ../assembler/assembler unittests/unit_test_file.asm unittests/unit_test_file.out

where `unit_test_file` is any of the unit test files (written in riscy-uconn assembly) in the
`unittests` directory.