From 03cbab84413c9d2ed9d6b863603071e3f860f31f Mon Sep 17 00:00:00 2001
From: cag-uconn <khan@uconn.edu>
Date: Thu, 10 Nov 2022 12:34:52 -0500
Subject: [PATCH] .

---
 pa3/src/sim_stages.c              | 10 ++++------
 pa3/unittests/branching_logic.asm |  2 +-
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/pa3/src/sim_stages.c b/pa3/src/sim_stages.c
index a28edb4..7b2fcfc 100644
--- a/pa3/src/sim_stages.c
+++ b/pa3/src/sim_stages.c
@@ -53,7 +53,6 @@ struct State fetch(struct State fetch_in) {
     return inst;
 }
 
-   
 /**
  * Decode stage implementation
  */
@@ -104,12 +103,12 @@ unsigned int writeback(struct State mem_out) {
 
 
 
+
 /* BRANCH PREDICTION FUNCTIONS*/
 
 /**
- * Branch Target Buffer Lookup:
+ * Branch target buffer lookup
  */
-
 unsigned int BTB_lookup(unsigned int inst_addr){
     int btb_hit = 0;
     
@@ -151,13 +150,12 @@ void predictor_update(unsigned int inst_addr, unsigned int branch_target, unsign
 
 
 
+
 /* DATA CACHE FUNCTIONS */
 
 /**
  * Data cache lookup
  */
-
-//Maybe increase cache size and just use memory addresses that force
 unsigned int dcache_lookup(unsigned int addr_mem) {
     int cache_hit = 0;
 
@@ -188,7 +186,7 @@ void update_simulator_state() {
     
     if (dmem_busy) {
         /* Stall every stage and overwrite memory for correct pipe trace */
-        mem_out = (struct State) {0};
+        mem_out = NOP;
 
     }else {
         /* Otherwise there is no memory stall and proceed pipeline as before */
diff --git a/pa3/unittests/branching_logic.asm b/pa3/unittests/branching_logic.asm
index 64b3972..63e614d 100644
--- a/pa3/unittests/branching_logic.asm
+++ b/pa3/unittests/branching_logic.asm
@@ -8,7 +8,7 @@ lw $a2, 2050($s0) # Load C from mem
 jal logic_gate
 sw $v0, 2051($s0)
 addi $s0, $s0, 4 # Increment index
-slti $t2, $s0, 16 # Set to 1 if i < 20
+slti $t2, $s0, 16 # Set to 1 if i < 16
 bne $t2, $zero, loop
 addi $zero, $zero, 1