diff --git a/pa1/Makefile b/pa1/Makefile deleted file mode 100644 index 9b8627c..0000000 --- a/pa1/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -SRCS = $(wildcard src/*.c) -HEADERS = $(wildcard src/*.h) -CC = gcc -CFLAGS = -g -std=c99 -LDFLAGS = -lm - -default: simulator - -simulator: $(SRCS) $(HEADERS) - @echo "Building $@..." - @#gcc simulator.o -o simulator -ggdb -std=c99 - @echo "Sources: $(SRCS)" - @echo "Headers: $(HEADERS)" - $(CC) $(CFLAGS) -o $@ $(SRCS) $(LDFLAGS) - -clean: - -rm -f simulator - -rm -f pipe_trace.txt *.out mdump.txt diff --git a/pa1/README.md b/pa1/README.md deleted file mode 100644 index 73b675d..0000000 --- a/pa1/README.md +++ /dev/null @@ -1,26 +0,0 @@ -# Programming Assignment 1: Non-pipelined riscy-uconn Simulator - -A non-pipelined CPU simulator for the MIPS-like riscy-uconn instruction set architecture. The -simulator translates machine code created by the riscy-uconn assembler, and executes instructions -one at a time. Each instruction goes through a Fetch, Decode, Execute, Memory and Writeback stage of -processing. - -## Build Instructions - $ make - -## Usage - $ ./simulator assembled_program_file.out - -where `assembled_program_file.out` may be any assembled program file generated by the riscy-uconn -assembler. - -## Unit Tests -Several unit tests are provided in the `unittests` directory. These unit tests must be assembled -before use with the simulator by executing the following command: - - $ ../assembler/assembler unittests/unit_test_file.asm unittests/unit_test_file.out - -where `unit_test_file` is any of the unit test files (written in riscy-uconn assembly) in the -`unittests` directory. - - diff --git a/pa1/src/instruction_map.c b/pa1/src/instruction_map.c deleted file mode 100644 index 9efb867..0000000 --- a/pa1/src/instruction_map.c +++ /dev/null @@ -1,40 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 1: Non-pipelined Simulator - * - * riscy-uconn: instruction_map.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include "instruction_map.h" - -char* opcode_map[] = { - [RTYPEOP] = "RTYPEOP", - [LW] = "lw", - [SW] = "sw", - [ANDI] = "andi", - [ADDI] = "addi", - [ORI] = "ori", - [SLTI] = "slti", - [LUI] = "lui", - [BEQ] = "beq", - [BNE] = "bne", - [J] = "j", - [JAL] = "jal" -}; - -char* func_map[] = { - [ADD] = "add", - [SUB] = "sub", - [AND] = "and", - [OR] = "or", - [SLL] = "sll", - [SRL] = "srl", - [SLT] = "slt", - [JR] = "jr" -}; \ No newline at end of file diff --git a/pa1/src/instruction_map.h b/pa1/src/instruction_map.h deleted file mode 100644 index b7b6261..0000000 --- a/pa1/src/instruction_map.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 1: Non-pipelined Simulator - * - * riscy-uconn: instruction_map.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -extern char* opcode_map[]; -extern char* func_map[]; - -/* R-Type Instructions */ -#define RTYPEOP 0x0 -#define ADD 0x20 -#define SUB 0x21 -#define AND 0x24 -#define OR 0x25 -#define SLL 0x0 -#define SLT 0x2A -#define SRL 0x2 -#define JR 0x8 - -/* I-Type Instructions */ -#define LW 0x23 -#define SW 0x2B -#define ANDI 0xC -#define ORI 0xD -#define LUI 0xF -#define BEQ 0x4 -#define BNE 0x5 -#define SLTI 0xA -#define ADDI 0x8 - -/* J-Type Instructions */ -#define J 0x2 -#define JAL 0x3 \ No newline at end of file diff --git a/pa1/src/register_map.c b/pa1/src/register_map.c deleted file mode 100644 index 0404a65..0000000 --- a/pa1/src/register_map.c +++ /dev/null @@ -1,49 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 1: Non-pipelined Simulator - * - * riscy-uconn: register_map.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include "register_map.h" - -const char* register_map[] = { - [0] = "zero", - [1] = "at", - [2] = "v0", - [3] = "v1", - [4] = "a0", - [5] = "a1", - [6] = "a2", - [7] = "a3", - [8] = "t0", - [9] = "t1", - [10] = "t2", - [11] = "t3", - [12] = "t4", - [13] = "t5", - [14] = "t6", - [15] = "t7", - [16] = "s0", - [17] = "s1", - [18] = "s2", - [19] = "s3", - [20] = "s4", - [21] = "s5", - [22] = "s6", - [23] = "s7", - [24] = "t8", - [25] = "t9", - [26] = "k0", - [27] = "k1", - [28] = "gp", - [29] = "sp", - [30] = "fp", - [31] = "ra", -}; \ No newline at end of file diff --git a/pa1/src/register_map.h b/pa1/src/register_map.h deleted file mode 100644 index 67cd567..0000000 --- a/pa1/src/register_map.h +++ /dev/null @@ -1,13 +0,0 @@ -#pragma once -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * riscy-uconn: register_map.h - * - * DO NOT MODIFY THIS FILE - * - */ - -extern const char* register_map[]; \ No newline at end of file diff --git a/pa1/src/sim_core.c b/pa1/src/sim_core.c deleted file mode 100644 index c1722c1..0000000 --- a/pa1/src/sim_core.c +++ /dev/null @@ -1,255 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 1: Non-pipelined Simulator - * - * riscy-uconn: sim_core.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include -#include -#include - -#include "instruction_map.h" -#include "register_map.h" -#include "sim_core.h" -#include "sim_stages.h" -#include "util.h" - -/** - * Initial CPU state - */ -int cycle = 0; // CPU cycle -int registers[MAX_LENGTH] = {0}; // Registers -unsigned int pc = 0; // Program Counter (PC) register -unsigned int pc_n = 0; -int *memory = NULL; // Data & instruction memory - -/** - * Utility - */ -FILE *fptr_pt; - -/** - * Simulator entry point - */ -int main(int argc, char *argv[]) { - if (argc != 2) { - fprintf(stderr, "[ERROR] incorrect number of arguments.\n"); - printf("usage: simulator PROGRAM_FILE\n"); - exit(1); - } else { - /* Open input program file */ - FILE *fp; - fp = fopen(argv[1], "r"); - - if (pipe_trace) { - fptr_pt = fopen("pipe_trace.txt", "w"); - } - - /* Initialize registers and instruction/data memory */ - initialize(fp); - - puts("\n"); - printf("Simulating...\n"); - - /* Process instructions one at a time */ - process_instructions(); - - puts(""); - - /* Output state after termination */ - rdump(); // Register dump - mdump(); // Memory dump - - /* Cleanup */ - free(memory); - fclose(fp); - if (pipe_trace) { - fclose(fptr_pt); - } - - return 0; - } -} - -void process_instructions() { - int terminate = 0; - int instruction_counter = 0; //committed instruction count - - while (terminate != 1) { - /* Initial cycle state */ - unsigned int fetch_out = 0xffffffff; - struct State decode_out = {0}; - struct State ex_out = {0}; - struct State mem_out = {0}; - - /* Fetch stage */ - fetch_out = fetch(fetch_out); - cycle++; - - if (pipe_trace == 1) { - fprintf(fptr_pt, "Cycle %d, PC %d: ", cycle, pc); - inst_dump("[Fetch]", fetch_out); - } - - /* Decode stage */ - decode_out = decode(fetch_out); - cycle++; - - if (pipe_trace == 1) { - fprintf(fptr_pt, "Cycle %d, PC %d: ", cycle, pc); - inst_dump("[Decode]", decode_out.inst); - } - - /* Execute stage */ - ex_out = execute(decode_out); - cycle++; - - if (pipe_trace == 1) { - fprintf(fptr_pt, "Cycle %d, PC %d: ", cycle, pc); - inst_dump("[Execute]", ex_out.inst); - } - - /* Memory stage */ - mem_out = memory_stage(ex_out); - cycle++; - - if (pipe_trace == 1) { - fprintf(fptr_pt, "Cycle %d, PC %d: ", cycle, pc); - inst_dump("[Memory]", mem_out.inst); - } - - /* Writeback stage */ - unsigned int committed_inst; - committed_inst = write_back_stage(mem_out); - cycle++; - - if (pipe_trace == 1) { - fprintf(fptr_pt, "Cycle %d, PC %d: ", cycle, pc); - inst_dump("[Writeback]", committed_inst); - fprintf(fptr_pt, "\n"); - rdump_pt(); - fprintf(fptr_pt, "\n"); - fprintf(fptr_pt, "=================================================================================================================================\n"); - fprintf(fptr_pt, "\n"); - } - - if (debug == 1) - fprintf(stderr, "[DEBUG] Cycle: %d, Instruction Memory Address: %d, Instruction: 0x%08x\n", cycle, pc / 4, fetch_out); - - if ((committed_inst != 0xffffffff) & (committed_inst != 0x00000000)) { - instruction_counter++; - } - - if (registers[0] != 0) { - terminate = 1; // set terminate flag when $zero is updated - } - - if (cycle == 10000) { - fprintf(stderr, "\n[WARNING] Simulation has simulated 10,000 cycles without terminating. Something might be wrong. Press CTRL + C to force termination.\n"); - } - - } - printf("\nFinished simulation!\n"); - printf("\nTOTAL INSTRUCTIONS COMMITTED: %d\n", instruction_counter); - printf("TOTAL CYCLES SIMULATED: %d\n", cycle); -} - -void initialize(FILE *fp) { - printf("======================================\n"); - printf("=== BEGIN SIMULATOR INITIALIZATION ===\n"); - printf("======================================\n"); - if (fp == NULL) { - fprintf(stderr, "[ERROR] opening input file. Aborting.\n"); - exit(1); - } - - /* Zero initialize registers */ - memset(registers, 0, sizeof(registers)); - printf("Initialized Registers\n"); - - /* Allocate instruction and data memory */ - memory = (int*) malloc(16384 * sizeof(int)); - if (memory == NULL) { - fprintf(stderr, "[ERROR] not enough memory. Aborting.\n"); - exit(1); - } - - /* Initialize memory to -1 */ - for (int i = 0; i < 16384; i++) { - memory[i] = -1; - } - printf("Initialized Memory\n"); - puts(""); - - printf("----------------------\n"); - printf("--- Section: .text ---\n"); - printf("----------------------\n"); - - /* Initialize parsing variables */ - char line[MAX_LENGTH + 2]; - char *p; - int i = 0, line_num = 0; - - /* Copy .text section to memory, break at nop */ - while (fgets(line, MAX_LENGTH + 2, fp) != NULL) { - line_num++; - - /* Remove '\n' from 'line' */ - p = strchr(line, '\n'); - if (p != NULL) { - *p = '\0'; - } - - memory[i] = getDec(line); - - /* If 'nop' found, move to 0x8000 / 2048 in memory and break */ - if (strcmp(line, "11111111111111111111111111111111") == 0) { - memory[i] = 0; - i = 0x800; - break; - } else { - printf("memory[%d] = 0x%08x\n", i, memory[i]); - i++; - } - } - - int j = 2048; //Data Memory Starts at 2048 - for (j = i; j < 16384; j++) { - memory[j] = 0; - } - - puts(""); - - printf("----------------------\n"); - printf("--- Section: .data ---\n"); - printf("----------------------\n"); - - /* Seek fp to first instruction in .data */ - char data[MAX_LENGTH + 2]; - int bytes = 33 * line_num; - fseek(fp, bytes, SEEK_SET); - - /* Copy .data section to memory */ - while (fgets(line, MAX_LENGTH + 2, fp) != NULL) { - /* Remove '\n' from 'line' */ - p = strchr(line, '\n'); - if (p != NULL) { - *p = '\0'; - } - - memory[i] = getDec(line); - printf("memory[%d] = 0x%08x\n", i, memory[i]); - i++; - } - - printf("====================================\n"); - printf("=== END SIMULATOR INITIALIZATION ===\n"); - printf("===================================="); -} diff --git a/pa1/src/sim_core.h b/pa1/src/sim_core.h deleted file mode 100644 index 6d3f3f6..0000000 --- a/pa1/src/sim_core.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 1: Non-pipelined Simulator - * - * riscy-uconn: sim_core.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -#include - -extern FILE *fptr_pt; - -/* Max number of registers, and instruction length in bits */ -#define MAX_LENGTH 32 - -/* Array of registers (register file) */ -extern int registers[MAX_LENGTH]; - -/* Clock cycle */ -extern int cycle; - -/* Program Counter (PC) register */ -extern unsigned int pc; // Current PC -extern unsigned int pc_n; // Next PC - -/* Instruction and data memory */ -extern int *memory; - -/* CPU state */ -struct State { - /* Fetched instruction */ - unsigned int inst; - - /* Decoded instruction fields */ - unsigned int opcode; - unsigned int func; - unsigned int rs; - unsigned int rt; - unsigned int rd; - unsigned int sa; - unsigned short imm; - - /* Memory related */ - unsigned int mem_flag; - unsigned int mem_addr; - unsigned int mem_out; - - /* JAL related */ - unsigned int jmp_out_31; - - /* ALU */ - unsigned int alu_in1; - unsigned int alu_in2; - unsigned int alu_out; -}; - -void initialize(FILE *fp); -void process_instructions(); \ No newline at end of file diff --git a/pa1/src/sim_stages.c b/pa1/src/sim_stages.c deleted file mode 100644 index cc24d3b..0000000 --- a/pa1/src/sim_stages.c +++ /dev/null @@ -1,83 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * YOUR NAME HERE - * - * Programming Assignment 1: Non-pipelined Simulator - * - * riscy-uconn: sim_stages.c - * - */ - -#include -#include -#include - -#include "instruction_map.h" -#include "sim_core.h" -#include "sim_stages.h" - -/** - * Debug flags - */ -int debug = 0; // Set to 1 for additional debugging information. -int pipe_trace = 1; // Set to 1 for pipe trace. - -/** - * Fetch stage implementation. - * DO NOT MODIFY. - */ -unsigned int fetch(unsigned int fetch_in) { - unsigned int inst = 0; - return inst = memory[pc / 4]; -} - -/** - * Decode stage implementation - */ -struct State decode(unsigned int fetch_out) { - struct State decode_out = {0}; - - /* Your code for the decode stage goes here. */ - - return decode_out; -} - -/** - * Execute stage implementation - */ -struct State execute(struct State decode_out) { - - /* Your code for the execute stage goes here. */ - - return decode_out; -} - -/** - * Memory stage implementation - */ -struct State memory_stage(struct State ex_out) { - - /* Your code for the memory stage goes here. */ - - return ex_out; -} - -/** - * Writeback stage implementation - */ -unsigned int write_back_stage(struct State mem_out) { - - /* Your code for the writeback stage goes here. */ - - return mem_out.inst; -} - -/** - * Advance PC. - * DO NOT MODIFY. - */ -void advance_pc(int step) { - pc += step; -} \ No newline at end of file diff --git a/pa1/src/sim_stages.h b/pa1/src/sim_stages.h deleted file mode 100644 index a5506ea..0000000 --- a/pa1/src/sim_stages.h +++ /dev/null @@ -1,26 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 1: Non-pipelined Simulator - * - * riscy-uconn: sim_stages.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -#include "sim_core.h" - -extern int debug; -extern int pipe_trace; - -unsigned int fetch(unsigned int instuction_fetch); -struct State decode(unsigned int instuction_fetch); -struct State execute(struct State decode_out); -struct State memory_stage(struct State alu_out); -unsigned int write_back_stage(struct State memory_out); -void advance_pc(int step); \ No newline at end of file diff --git a/pa1/src/util.c b/pa1/src/util.c deleted file mode 100644 index 921696a..0000000 --- a/pa1/src/util.c +++ /dev/null @@ -1,208 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 1: Non-pipelined Simulator - * - * riscy-uconn: util.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include -#include -#include -#include -#include - -#include "instruction_map.h" -#include "register_map.h" -#include "sim_core.h" - -/** - * Dump register contents. - * Will format for desired number of columns and output in specified file. - */ -void rdump_file_columns(FILE* file, unsigned columns) { - static const unsigned int index_col_width = 4; - static const unsigned int name_col_width = 5; - static const unsigned int value_col_width = 8; - static const unsigned int tab_spaces = 4; - static const unsigned int col_sep = 2; - - assert(columns > 0); - - /* Calculate number of rows and total row length*/ - const unsigned int rows = (int)ceil((double) MAX_LENGTH / columns); - const unsigned int row_length = columns * (index_col_width + name_col_width + value_col_width + 2 + 2 * tab_spaces) + (columns - 1) * (col_sep * tab_spaces); - - /* Print header */ - fprintf(file, "---------------------\n"); - fprintf(file, "--- Register Dump ---\n"); - fprintf(file, "---------------------\n"); - for (int col = 0; col < columns; col++) { - fprintf(file, "%-*s%-*s%-*s", index_col_width + tab_spaces, "Index", name_col_width + tab_spaces, "Name", value_col_width + 2, "Value"); - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - for (int col = 0; col < columns; col++) { - fprintf(file, "%-*s%-*s%-*s", index_col_width + tab_spaces, "-----", name_col_width + tab_spaces, "----", value_col_width + 2, "-----"); - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - - /* Print rows */ - for (int row = 0; row < rows; row++) { - for (int col = 0; col < columns; col++) { - unsigned int i = row + col * rows; - - if (i < MAX_LENGTH) { - fprintf(file, "$%-*i%*s$%-*s%*s0x%0*x", index_col_width, i, tab_spaces - 1, "", name_col_width, register_map[i], tab_spaces - 1, "", value_col_width, registers[i]); - } else { - fprintf(file, "\n"); - break; - } - - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - } - fprintf(file, "%-*s%*s%-*s%*s0x%08x\n", index_col_width, "N/A", tab_spaces, "", name_col_width, "pc", tab_spaces, "", pc); -} - -void rdump_pt() { - rdump_file_columns(fptr_pt, 4); -} - -void rdump() { - rdump_file_columns(stdout, 4); -} - -/** - * Dump memory contents. - */ -void mdump() { - FILE* fptr; - fptr = fopen("mdump.txt", "w"); - int i = 0; - for (i = 0; i < 16384; i++) { - fprintf(fptr, "Memory[%d] = 0x%08x\n", i, memory[i]); - } - fclose(fptr); -} - -void inst_dump(const char stage[], const unsigned int inst) { - int opcode = inst >> 26; - - unsigned int func = inst << 26; - func = func >> 26; - - int rs = (inst >> 21) & 0x1F; - int rt = (inst >> 16) & 0x1F; - int rd = (inst >> 11) & 0x1F; - int sa = (inst >> 6) & 0x1F; - int imm = inst & 0xFFFF; - short shortImm = (short)imm; - int target = inst & 0x03ffffff; - - fprintf(fptr_pt, "%-12s ", stage); - - if (inst == 0xffffffff) { - fprintf(fptr_pt, "INVALID INSTRUCTION\n"); - } - - switch (opcode) { - case RTYPEOP: - switch (func) { - case JR: - fprintf(fptr_pt, "%-4s %d\n", func_map[func], rs); - break; - - case SLL: - case SRL: - fprintf(fptr_pt, "%-4s $%d, $%d, %d\n", func_map[func], rd, rt, sa); - break; - - case ADD: - case SUB: - case AND: - case OR: - case SLT: - fprintf(fptr_pt, "%-4s $%d, $%d, $%d\n", func_map[func], rd, rs, rt); - break; - - default: - fprintf(fptr_pt, "INVALID INSTRUCTION\n"); - break; - } - break; - - case LW: - case SW: - fprintf(fptr_pt, "%-4s $%d %d($%d)\n", opcode_map[opcode], rt, imm, rs); - break; - - case ANDI: - case ADDI: - case ORI: - case SLTI: - fprintf(fptr_pt, "%-4s $%d, $%d, %d\n", opcode_map[opcode], rt, rs, imm); - break; - - case LUI: - fprintf(fptr_pt, "%-4s $%d, %d\n", opcode_map[opcode], rt, imm); - break; - - case BEQ: - case BNE: - fprintf(fptr_pt, "%-4s $%d, $%d, %d\n", opcode_map[opcode], rs, rt, shortImm); - break; - - case J: - case JAL: - fprintf(fptr_pt, "%-4s %d", opcode_map[opcode], target); - break; - - default: - fprintf(fptr_pt, "INVALID INSTRUCTION\n"); - break; - } -} - -// Convert a binary string to a decimal value -int getDec(char *bin) { - int b, k, m, n; - int len, sum = 0; - - // Length - 1 to accomodate for null terminator - len = strlen(bin) - 1; - - // Iterate the string - for (k = 0; k <= len; k++) { - // Convert char to numeric value - n = (bin[k] - '0'); - - // Check the character is binary - if ((n > 1) || (n < 0)) { - return 0; - } - - for (b = 1, m = len; m > k; m--) - b *= 2; - - // sum it up - sum = sum + n * b; - } - return sum; -} \ No newline at end of file diff --git a/pa1/src/util.h b/pa1/src/util.h deleted file mode 100644 index f744c8f..0000000 --- a/pa1/src/util.h +++ /dev/null @@ -1,23 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 1: Non-pipelined Simulator - * - * riscy-uconn: util.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -#include - -void rdump_file_columns(FILE* file, unsigned columns); -void rdump(); -void rdump_pt(); -void mdump(); -void inst_dump(const char stage[], const unsigned int inst); -int getDec(char *bin); \ No newline at end of file diff --git a/pa1/unittests/.gitignore b/pa1/unittests/.gitignore deleted file mode 100644 index e2e7327..0000000 --- a/pa1/unittests/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/out diff --git a/pa1/unittests/beq_test1.asm b/pa1/unittests/beq_test1.asm deleted file mode 100644 index 758bdc7..0000000 --- a/pa1/unittests/beq_test1.asm +++ /dev/null @@ -1,27 +0,0 @@ -.text -add $a0, $zero, $zero # set $a0=0 : 0 --> i -addi $a1, $zero, 1 # set $a1=1 - -loop: -addi $t0, $zero, 2048 # set $t0 to 2048 -#ori $t0, $zero, 2048 # set $t0 to 2048 -sll $t1, $a0, 2 # $t1 <-- $a0 << 2 : $t1 <-- i*4 -add $t0, $t0, $t1 # form address of array[i] in $t0 -sw $zero, 0($t0) # store 32-bits of zero from $zero into array[i] -addi $a0, $a0, 1 # i++ -slti $t0, $a0, 10 # set $t0=1 if $a0 < 10 otherwise $t0=0 -beq $t0, $a1, loop # if $t0=0, branch to end label - -addi $zero $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 10 -2049: .word 32 -2050: .word 2 -2051: .word 2 -2052: .word 5 -2053: .word 5 -2054: .word 5 -2055: .word 5 -2056: .word 5 - diff --git a/pa1/unittests/beq_test2.asm b/pa1/unittests/beq_test2.asm deleted file mode 100644 index 30dbdb0..0000000 --- a/pa1/unittests/beq_test2.asm +++ /dev/null @@ -1,27 +0,0 @@ -.text -add $a0, $zero, $zero # set $a0=0 : 0 --> i - -loop: -slti $t0, $a0, 10 # set $t0=1 if $a0 < 10 otherwise $t0=0 -beq $t0, $zero, end # if $t0=0, branch to end label -addi $t0, $zero, 2048 -sll $t1, $a0, 2 # $t1 <-- $a0 << 2 : $t1 <-- i*4 -add $t0, $t0, $t1 # form address of array[i] in $t0 -sw $zero, 0($t0) # store 32-bits of zero from $zero into array[i] -addi $a0, $a0, 1 # i++ -beq $zero, $zero, loop # branch to label loop -- always branches - -end: -addi $zero $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 10 -2049: .word 32 -2050: .word 2 -2051: .word 2 -2052: .word 5 -2053: .word 5 -2054: .word 5 -2055: .word 5 -2056: .word 5 - diff --git a/pa1/unittests/bne_test1.asm b/pa1/unittests/bne_test1.asm deleted file mode 100644 index fb354d8..0000000 --- a/pa1/unittests/bne_test1.asm +++ /dev/null @@ -1,28 +0,0 @@ -.text -add $a0, $zero, $zero # set $a0=0 : 0 --> i - -loop: -#addi $t0, $zero, 2048 # set $t0 to 2048 -ori $t0, $zero, 2048 # set $t0 to 2048 -#lui $t0, 0 # $t0 <-- 0x00000000 -#ori $t0, $t0, 0 # $t0 <-- $t0 | 0x0800 : $t0 = 0x00000800 -sll $t1, $a0, 2 # $t1 <-- $a0 << 2 : $t1 <-- i*4 -add $t0, $t0, $t1 # form address of array[i] in $t0 -sw $zero, 0($t0) # store 32-bits of zero from $zero into array[i] -addi $a0, $a0, 1 # i++ -slti $t0, $a0, 10 # set $t0=1 if $a0 < 10 otherwise $t0=0 -bne $t0, $zero, loop # if $t0=0, branch to end label - -addi $zero $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 10 -2049: .word 32 -2050: .word 2 -2051: .word 2 -2052: .word 5 -2053: .word 5 -2054: .word 5 -2055: .word 5 -2056: .word 5 - diff --git a/pa1/unittests/fibonacci.asm b/pa1/unittests/fibonacci.asm deleted file mode 100644 index f086574..0000000 --- a/pa1/unittests/fibonacci.asm +++ /dev/null @@ -1,50 +0,0 @@ -.text -addi $t9, $zero, 10 -addi $t1, $zero, 0 -addi $t2, $zero, 1 -j fibonacci - -fibonacci: -add $t3, $t2, $t1 -add $t1, $zero, $t2 -add $t2, $zero, $t3 -addi $t5, $t5, 1 -bne $t5, $t9, fibonacci -addi $zero $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 10 -2049: .word 10 -2050: .word 20 -2051: .word 30 -2052: .word 40 -2053: .word 50 -2054: .word 60 -2055: .word 70 -2056: .word 80 -2057: .word 90 -2058: .word 100 -2059: .word 3 -2060: .word 3 -2061: .word 3 -2062: .word 3 -2063: .word -2064: .word 11 -2065: .word 10 -2066: .word 20 -2067: .word 30 -2068: .word 40 -2069: .word 50 -2070: .word 60 -2071: .word 70 -2072: .word 80 -2073: .word 90 -2074: .word 100 -2075: .word 3 -2076: .word 3 -2077: .word 3 -2078: .word 3 -2079: .word 3 -2080: .word 5 - - diff --git a/pa1/unittests/j_test1.asm b/pa1/unittests/j_test1.asm deleted file mode 100644 index 550fcb0..0000000 --- a/pa1/unittests/j_test1.asm +++ /dev/null @@ -1,27 +0,0 @@ -.text -add $t0, $zero, $zero # iterator i = 0 -add $t2, $zero, $zero # initialize a memory pointer to zero -add $t3, $zero, $zero # initialize temporary register to zero -add $t4, $zero, $zero # initialize temporary register to zero -j jump_test1 # Jump to procedure "jump_test1" - -jump_test2: -lw $a1, 2048($t2) # Load a1 = 2, Mem[2048] = 2, 2 in simulator -addi $t2, $t2, 1 # Add 1 to the pointer to access Mem[2049] -lw $a2, 2048($t2) # Load a2 = 10, Mem[2049] = 10, 10 in simulator -j end # Jump to procedure "end" - -jump_test1: -add $t5, $zero, $zero # initialize temporary register to zero -add $t6, $zero, $zero # initialize temporary register to zero -j jump_test2 # Jump to procedure "jump_test2" - -end: -addi $zero $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -# --- Start of the Memory Layout --- - -.data -2048: .word 2 -2049: .word 10 - diff --git a/pa1/unittests/jal_test1.asm b/pa1/unittests/jal_test1.asm deleted file mode 100644 index 091d4a1..0000000 --- a/pa1/unittests/jal_test1.asm +++ /dev/null @@ -1,20 +0,0 @@ -.text -addi $a0, $zero, 2 # argument 0 = 2 -addi $a1, $zero, 3 # argument 1 = 3 -addi $a2, $zero, 4 # argument 2 = 4 -addi $a3, $zero, 5 # argument 3 = 5 -add $t4, $zero, $zero -jal diffofsums # call procedure -add $s0, $v0, $zero # y = returned value -addi $zero $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -diffofsums: -add $t0, $a0, $a1 # $t0 = f + g -add $t1, $a2, $a3 # $t1 = h + i -sub $s0, $t0, $t1 # result = (f+g)-(h+i) -add $v0, $s0, $zero # put return value in $v0 -jr $ra # return to caller - -.data -2048: .word 10 -2049: .word 10 diff --git a/pa1/unittests/jr_test1.asm b/pa1/unittests/jr_test1.asm deleted file mode 100644 index f465759..0000000 --- a/pa1/unittests/jr_test1.asm +++ /dev/null @@ -1,24 +0,0 @@ -.text -addi $a0, $zero, 2 # argument 0 = 2 -addi $a1, $zero, 3 # argument 1 = 3 -addi $a2, $zero, 4 # argument 2 = 4 -addi $a3, $zero, 5 # argument 3 = 5 -add $t4, $zero, $zero -addi $t4, $t4, 44 -jr $t4 # call procedure -add $s0, $v0, $zero # y = returned value -add $t5, $zero, $zero -addi $t5, $t5, 72 -jr $t5 -add $t0, $a0, $a1 # $t0 = f + g -add $t1, $a2, $a3 # $t1 = h + i -sub $s0, $t0, $t1 # result = (f+g)-(h+i) -add $v0, $s0, $zero # put return value in $v0 -add $t6, $zero, $zero -addi $t6, $t6, 28 -jr $t6 # return to caller -addi $zero $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 10 -2049: .word 10 diff --git a/pa1/unittests/jr_test2.asm b/pa1/unittests/jr_test2.asm deleted file mode 100644 index f9b504c..0000000 --- a/pa1/unittests/jr_test2.asm +++ /dev/null @@ -1,21 +0,0 @@ -.text -addi $a0, $zero, 2 # argument 0 = 2 -addi $a1, $zero, 3 # argument 1 = 3 -addi $a2, $zero, 4 # argument 2 = 4 -addi $a3, $zero, 5 # argument 3 = 5 -add $t4, $zero, $zero -addi $t4, $t4, 36 -jr $t4 # call procedure -add $s0, $v0, $zero # y = returned value -addi $zero $zero, 1 # $zero register should never be updated, so detect this change and quit simulator -add $t0, $a0, $a1 # $t0 = f + g -add $t1, $a2, $a3 # $t1 = h + i -sub $s0, $t0, $t1 # result = (f+g)-(h+i) -add $v0, $s0, $zero # put return value in $v0 -add $t6, $zero, $zero -addi $t6, $t6, 28 -jr $t6 # return to caller - -.data -2048: .word 10 -2049: .word 10 diff --git a/pa1/unittests/lw_sw_test1.asm b/pa1/unittests/lw_sw_test1.asm deleted file mode 100644 index dcb79f0..0000000 --- a/pa1/unittests/lw_sw_test1.asm +++ /dev/null @@ -1,59 +0,0 @@ -.text -add $t0, $zero, $zero # i = 0 -add $t1, $zero, $zero # initialize the sum to zero -add $t2, $zero, $zero # for second loop compare 2 -add $t3, $zero, $zero -add $t5, $zero, $zero # initialize temporary register to zero -add $t6, $zero, $zero # for sw later -add $t7, $zero, $zero - -lw $t1, 2048($t0) # $t1=20 -lw $t2, 2048($t1) # $t2=4 -add $t4, $t1, $t2 # $t4=24 -lw $t3, 2048($t4) # $t3=8 -add $t4, $t4, $t3 # $t4=32 -sw $t4, 2048($t0) # mem[2048]=32 -lw $t1, 2048($t0) # $t1=32 <-- observation of stored value 32 as $t1=0x00000020 -lw $t2, 2048($t1) # $t2=5 -add $t4, $t1, $t2 # $t4=37 -sw $t4, 2048($t1) # mem[2080]=37 -lw $t5, 2048($t1) # $t5=37 <--- observation of stored value 37 as $t5=0x00000025 - -addi $zero $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 20 -2049: .word 32 -2050: .word 2 -2051: .word 2 -2052: .word 3 -2053: .word 3 -2054: .word 3 -2055: .word 3 -2056: .word 3 -2057: .word 3 -2058: .word 3 -2059: .word 3 -2060: .word 3 -2061: .word 3 -2062: .word 3 -2063: .word 3 -2064: .word 3 -2065: .word 3 -2066: .word 3 -2067: .word 3 -2068: .word 4 -2069: .word 3 -2070: .word 3 -2071: .word 3 -2072: .word 8 -2073: .word 3 -2074: .word 3 -2075: .word 3 -2076: .word 3 -2077: .word 3 -2078: .word 3 -2079: .word 3 -2080: .word 5 - - diff --git a/pa1/unittests/rand_test1.asm b/pa1/unittests/rand_test1.asm deleted file mode 100644 index 4f63409..0000000 --- a/pa1/unittests/rand_test1.asm +++ /dev/null @@ -1,38 +0,0 @@ -.text -add $t0, $zero, $zero -add $t1, $zero, $zero -add $t2, $zero, $zero -add $t3, $zero, $zero -add $t5, $zero, $zero -add $t6, $zero, $zero -add $t7, $zero, $zero - - -lw $t1, 2048($t0) # $t1=5119 or 0x000013ff -andi $t2, $t1, 255 # mask 0x000000ff, so $t2=255 or 0x000000ff -sll $t3, $t2, 1 # times 2, so $t3=510 or 0x000001fe -andi $t4, $t3, 63 # mask 0x0000003f, so $t4=62 or 0x0000003e -#lui $t5, 65535 # $t5=-65536 or 0xffff0000 - -srl $t5, $t4, 1 # div 2, so $t5=31 or 0x0000001f -srl $t6, $t4, 2 # div 4, so $t6=15 or 0x0000000f -srl $t7, $t4, 3 # div 8, so $t7=7 or 0x00000007 - -sub $a0, $t5, $t6 # $a0=16 or 0x00000010 -and $a1, $t5, $t6 # $a1=15 or 0x0000000f -or $a2, $t5, $t6 # $a2=31 or 0x0000001f - - -ori $a3, $a0, 3 # $a3=19 or 0x00000013 - -slti $t0, $a0, 17 # $t0=1 -addi $t0, $t0, 2 # $t0=3 or 0x00000003 - -addi $zero $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - - -.data -2048: .word 5119 -2049: .word 32 - - diff --git a/pa1/unittests/rand_test2.asm b/pa1/unittests/rand_test2.asm deleted file mode 100644 index d3f8f7b..0000000 --- a/pa1/unittests/rand_test2.asm +++ /dev/null @@ -1,23 +0,0 @@ -.text -add $t0, $zero, $zero -add $t1, $zero, $zero -add $t2, $zero, $zero -add $t3, $zero, $zero -add $t5, $zero, $zero -add $t6, $zero, $zero -add $t7, $zero, $zero - - -lw $t1, 2048($t0) # $t1=5119 or 0x000013ff -andi $t2, $t1, 255 # mask 0x000000ff, so $t2=255 or 0x000000ff -sll $t3, $t2, 1 # times 2, so $t3=510 or 0x000001fe -andi $t4, $t3, 63 # mask 0x0000003f, so $t4=62 or 0x0000003e -lui $t5, 65535 # $t5=-65536 or 0xffff0000 - -addi $zero $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 5119 -2049: .word 32 - - diff --git a/pa2/Makefile b/pa2/Makefile deleted file mode 100644 index 906d10f..0000000 --- a/pa2/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -SRCS = $(wildcard src/*.c) -HEADERS = $(wildcard src/*.h) -CC = gcc -CFLAGS = -g -std=c99 -LDFLAGS = -lm - -default: simulator - -simulator: $(SRCS) $(HEADERS) - @echo "Building $@..." - @echo "Sources: $(SRCS)" - @echo "Headers: $(HEADERS)" - $(CC) $(CFLAGS) -o $@ $(SRCS) $(LDFLAGS) - -clean: - -rm -f simulator - -rm -f pipe_trace.txt *.out mdump.txt diff --git a/pa2/README.md b/pa2/README.md deleted file mode 100644 index 25ee6a8..0000000 --- a/pa2/README.md +++ /dev/null @@ -1,26 +0,0 @@ -# Programming Assignment 2: Pipelined riscy-uconn Simulator - -A 5-stage pipelined CPU simulator for the MIPS-like riscy-uconn instruction set architecture. The -simulator translates machine code created by the riscy-uconn assembler, and executes instructions -one at a time. Each instruction goes through a Fetch, Decode, Execute, Memory and Writeback stage of -processing. - -## Build Instructions - $ make - -## Usage - $ ./simulator assembled_program_file.out FORWARDING_ENABLED - -where `assembled_program_file.out` may be any assembled program file generated by the riscy-uconn -assembler, and `FORWARDING_ENABLED` may be 0 (disabled) or 1 (enabled). - -## Unit Tests -Several unit tests are provided in the `unittests` directory. These unit tests must be assembled -before use with the simulator by executing the following command: - - $ ../assembler/assembler unittests/unit_test_file.asm unittests/unit_test_file.out - -where `unit_test_file` is any of the unit test files (written in riscy-uconn assembly) in the -`unittests` directory. - - diff --git a/pa2/src/instruction_map.c b/pa2/src/instruction_map.c deleted file mode 100644 index 8a47f93..0000000 --- a/pa2/src/instruction_map.c +++ /dev/null @@ -1,40 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 2: Pipelined Simulator - * - * riscy-uconn: instruction_map.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include "instruction_map.h" - -char* opcode_map[] = { - [RTYPEOP] = "RTYPEOP", - [LW] = "lw", - [SW] = "sw", - [ANDI] = "andi", - [ADDI] = "addi", - [ORI] = "ori", - [SLTI] = "slti", - [LUI] = "lui", - [BEQ] = "beq", - [BNE] = "bne", - [J] = "j", - [JAL] = "jal" -}; - -char* func_map[] = { - [ADD] = "add", - [SUB] = "sub", - [AND] = "and", - [OR] = "or", - [SLL] = "sll", - [SRL] = "srl", - [SLT] = "slt", - [JR] = "jr" -}; \ No newline at end of file diff --git a/pa2/src/instruction_map.h b/pa2/src/instruction_map.h deleted file mode 100644 index 5666db3..0000000 --- a/pa2/src/instruction_map.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 2: Pipelined Simulator - * - * riscy-uconn: instruction_map.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -extern char* opcode_map[]; -extern char* func_map[]; - -/* R-Type Instructions */ -#define RTYPEOP 0x0 -#define ADD 0x20 -#define SUB 0x21 -#define AND 0x24 -#define OR 0x25 -#define SLL 0x0 -#define SLT 0x2A -#define SRL 0x2 -#define JR 0x8 - -/* I-Type Instructions */ -#define LW 0x23 -#define SW 0x2B -#define ANDI 0xC -#define ORI 0xD -#define LUI 0xF -#define BEQ 0x4 -#define BNE 0x5 -#define SLTI 0xA -#define ADDI 0x8 - -/* J-Type Instructions */ -#define J 0x2 -#define JAL 0x3 \ No newline at end of file diff --git a/pa2/src/register_map.c b/pa2/src/register_map.c deleted file mode 100644 index 054cbe6..0000000 --- a/pa2/src/register_map.c +++ /dev/null @@ -1,49 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 2: Pipelined Simulator - * - * riscy-uconn: register_map.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include "register_map.h" - -const char* register_map[] = { - [0] = "zero", - [1] = "at", - [2] = "v0", - [3] = "v1", - [4] = "a0", - [5] = "a1", - [6] = "a2", - [7] = "a3", - [8] = "t0", - [9] = "t1", - [10] = "t2", - [11] = "t3", - [12] = "t4", - [13] = "t5", - [14] = "t6", - [15] = "t7", - [16] = "s0", - [17] = "s1", - [18] = "s2", - [19] = "s3", - [20] = "s4", - [21] = "s5", - [22] = "s6", - [23] = "s7", - [24] = "t8", - [25] = "t9", - [26] = "k0", - [27] = "k1", - [28] = "gp", - [29] = "sp", - [30] = "fp", - [31] = "ra", -}; \ No newline at end of file diff --git a/pa2/src/register_map.h b/pa2/src/register_map.h deleted file mode 100644 index 871c5ea..0000000 --- a/pa2/src/register_map.h +++ /dev/null @@ -1,16 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 2: Pipelined Simulator - * - * riscy-uconn: register_map.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -extern const char* register_map[]; \ No newline at end of file diff --git a/pa2/src/sim_core.c b/pa2/src/sim_core.c deleted file mode 100644 index e01e4d6..0000000 --- a/pa2/src/sim_core.c +++ /dev/null @@ -1,250 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 2: Pipelined Simulator - * - * riscy-uconn: sim_core.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include -#include -#include - -#include "instruction_map.h" -#include "register_map.h" -#include "sim_core.h" -#include "sim_stages.h" -#include "util.h" - -/** - * Initial CPU state - */ -int cycle = 0; // CPU cycle -int registers[MAX_LENGTH] = {0}; // Registers -unsigned int pc = 0; // Program Counter (PC) register -unsigned int pc_n = 0; -int *memory = NULL; // Data & instruction memory - -/** - * Utility - */ -FILE *fptr_pt; - -/* Pipeline related */ -int forwarding_enabled = 0; - -/** - * Simulator entry point - */ -int main(int argc, char *argv[]) { - if (argc != 3) { - fprintf(stderr, "[ERROR] incorrect number of arguments.\n"); - printf("usage: simulator PROGRAM_FILE FORWARDING_ENABLED\n"); - exit(1); - } else { - /* Open input program file */ - FILE *fp; - fp = fopen(argv[1], "r"); - - /* Enable/disable forwarding */ - sscanf(argv[2],"%d",&forwarding_enabled); - if (forwarding_enabled > 1) { - fprintf(stderr, "[ERROR] FORWARDING_ENABLED must be either 0 (disabled) or 1 (enabled).\n"); - exit(1); - } - printf("Pipeline Forwarding: %s\n", forwarding_enabled ? "Enabled" : "Disabled"); - - /* Open pipe trace */ - if (pipe_trace) { - fptr_pt = fopen("pipe_trace.txt", "w"); - } - - /* Initialize registers and instruction/data memory */ - initialize(fp); - - puts("\n"); - printf("Simulating...\n"); - - /* Process instructions one at a time */ - process_instructions(); - - puts(""); - - /* Output state after termination */ - rdump(); // Register dump - mdump(); // Memory dump - - /* Cleanup */ - free(memory); - fclose(fp); - if (pipe_trace) { - fclose(fptr_pt); - } - - return 0; - } -} - -void process_instructions() { - int terminate = 0; - int instruction_counter = 0; //committed instruction count - - /* Initialize pipeline state */ - unsigned int committed_inst; - unsigned int fetch_out = -1, fetch_out_n; - struct State decode_out = {-1}, decode_out_n; - struct State ex_out = {-1}, ex_out_n; - struct State mem_out = {-1}, mem_out_n; - - while (terminate != 1) { - /* Update pipeline state */ - committed_inst = write_back_stage(mem_out); - mem_out_n = memory_stage(ex_out); - ex_out_n = execute(decode_out); - decode_out_n = decode(fetch_out); - fetch_out_n = fetch(fetch_out); - - if (pipe_trace == 1) { - fprintf(fptr_pt, "Cycle %d, PC %d, Next PC %d\n", cycle, pc, pc_n); - inst_dump("[Fetch]", fetch_out_n); - inst_dump("[Decode]", decode_out_n.inst); - inst_dump("[Execute]", ex_out_n.inst); - inst_dump("[Memory]", mem_out_n.inst); - inst_dump("[Writeback]", committed_inst); - fprintf(fptr_pt, "\n"); - rdump_pt(); - fprintf(fptr_pt, "\n"); - fprintf(fptr_pt, "=================================================================================================================================\n"); - fprintf(fptr_pt, "\n"); - } - - if (debug) { - fprintf(stderr, "[DEBUG] Cycle: %d, Instruction Memory Address: %d, Instruction: 0x%08x\n", cycle, pc / 4, fetch_out_n); - } - - if ((committed_inst != 0xffffffff) & (committed_inst != 0x00000000)) { - instruction_counter++; - } - - if (debug) { - fprintf(stderr, "[DEBUG] Cycle: %d, Committed Instruction: 0x%08x\n", cycle, committed_inst); - } - - if (registers[0] != 0) { - terminate = 1; // set terminate flag when $zero is updated - } - - /* Update state for next cycle */ - pc = pc_n; - fetch_out = fetch_out_n; - decode_out = decode_out_n; - ex_out = ex_out_n; - mem_out = mem_out_n; - cycle++; - - if (cycle == 10000) { - fprintf(stderr, "\n[WARNING] Simulation has simulated 10,000 cycles without terminating. Something might be wrong. Press CTRL + C to force termination.\n"); - } - } - printf("\nFinished simulation!\n"); - printf("\nTOTAL INSTRUCTIONS COMMITTED: %d\n", instruction_counter); - printf("TOTAL CYCLES SIMULATED: %d\n", cycle); -} - -void initialize(FILE *fp) { - printf("======================================\n"); - printf("=== BEGIN SIMULATOR INITIALIZATION ===\n"); - printf("======================================\n"); - if (fp == NULL) { - fprintf(stderr, "[ERROR] opening input file. Aborting.\n"); - exit(1); - } - - /* Zero initialize registers */ - memset(registers, 0, sizeof(registers)); - printf("Initialized Registers\n"); - - /* Allocate instruction and data memory */ - memory = (int*) malloc(16384 * sizeof(int)); - if (memory == NULL) { - fprintf(stderr, "[ERROR] not enough memory. Aborting.\n"); - exit(1); - } - - /* Initialize memory to -1 */ - for (int i = 0; i < 16384; i++) { - memory[i] = -1; - } - printf("Initialized Memory\n"); - puts(""); - - printf("----------------------\n"); - printf("--- Section: .text ---\n"); - printf("----------------------\n"); - - /* Initialize parsing variables */ - char line[MAX_LENGTH + 2]; - char *p; - int i = 0, line_num = 0; - - /* Copy .text section to memory, break at nop */ - while (fgets(line, MAX_LENGTH + 2, fp) != NULL) { - line_num++; - - /* Remove '\n' from 'line' */ - p = strchr(line, '\n'); - if (p != NULL) { - *p = '\0'; - } - - memory[i] = getDec(line); - - /* If 'nop' found, move to 0x800 / 2048 in memory and break */ - if (strcmp(line, "11111111111111111111111111111111") == 0) { - memory[i] = 0; - i = 0x800; - break; - } else { - printf("memory[%d] = 0x%08x\n", i, memory[i]); - i++; - } - } - - int j = 2048; //Data Memory Starts at 2048 - for (j = i; j < 16384; j++) { - memory[j] = 0; - } - - puts(""); - - printf("----------------------\n"); - printf("--- Section: .data ---\n"); - printf("----------------------\n"); - - /* Seek fp to first instruction in .data */ - char data[MAX_LENGTH + 2]; - int bytes = 33 * line_num; - fseek(fp, bytes, SEEK_SET); - - /* Copy .data section to memory */ - while (fgets(line, MAX_LENGTH + 2, fp) != NULL) { - /* Remove '\n' from 'line' */ - p = strchr(line, '\n'); - if (p != NULL) { - *p = '\0'; - } - - memory[i] = getDec(line); - printf("memory[%d] = 0x%08x\n", i, memory[i]); - i++; - } - - printf("====================================\n"); - printf("=== END SIMULATOR INITIALIZATION ===\n"); - printf("===================================="); -} diff --git a/pa2/src/sim_core.h b/pa2/src/sim_core.h deleted file mode 100644 index 730b72c..0000000 --- a/pa2/src/sim_core.h +++ /dev/null @@ -1,75 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 2: Pipelined Simulator - * - * riscy-uconn: sim_core.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -#include - -extern FILE *fptr_pt; - -/* Max number of registers, and instruction length in bits */ -#define MAX_LENGTH 32 - -/* Array of registers (register file) */ -extern int registers[MAX_LENGTH]; - -/* Clock cycle */ -extern int cycle; - -/* Program Counter (PC) register */ -extern unsigned int pc; // Current PC -extern unsigned int pc_n; // Next PC - -/* Instruction and data memory */ -extern int *memory; - -/* CPU state */ -struct State { - /* Fetched instruction */ - unsigned int inst; - - /* Decoded instruction fields */ - unsigned int opcode; - unsigned int func; - unsigned int rs; - unsigned int rt; - unsigned int rd; - unsigned int sa; - unsigned short imm; - - /* Memory related */ - unsigned int mem_flag; - unsigned int mem_addr; - unsigned int mem_out; - - /* JAL related */ - unsigned int jmp_out_31; - - /* ALU */ - unsigned int alu_in1; - unsigned int alu_in2; - unsigned int alu_out; -}; - -/* Pipeline related */ -extern int forwarding_enabled; -extern int pipe_stall; -extern int br_taken; -extern int lw_in_exe; -extern int we_exe, ws_exe, dout_exe; -extern int we_mem, ws_mem, dout_mem; -extern int we_wb, ws_wb, dout_wb; - - -void initialize(FILE *fp); -void process_instructions(); \ No newline at end of file diff --git a/pa2/src/sim_stages.c b/pa2/src/sim_stages.c deleted file mode 100644 index ebc1801..0000000 --- a/pa2/src/sim_stages.c +++ /dev/null @@ -1,90 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * YOUR NAME HERE - * - * Programming Assignment 2: Pipelined Simulator - * - * riscy-uconn: sim_stages.c - * - */ - -#include -#include -#include - -#include "instruction_map.h" -#include "sim_core.h" -#include "sim_stages.h" - -/** - * Debug flags - */ -int debug = 0; // Set to 1 for additional debugging information. -int pipe_trace = 1; // Set to 1 for pipe trace. - -/* Pipeline related */ -int pipe_stall = 0; -int br_taken = 0; -int lw_in_exe = 0; -int we_exe = 0, ws_exe = 0, dout_exe = 0; -int we_mem = 0, ws_mem = 0, dout_mem = 0; -int we_wb = 0, ws_wb = 0, dout_wb = 0; - -/** - * Fetch stage implementation. - */ -unsigned int fetch(unsigned int fetch_in) { - unsigned int inst = 0; - return inst = memory[pc / 4]; -} - -/** - * Decode stage implementation - */ -struct State decode(unsigned int fetch_out) { - struct State decode_out = {0}; - - /* Your code for the decode stage goes here. */ - - return decode_out; -} - -/** - * Execute stage implementation - */ -struct State execute(struct State decode_out) { - - /* Your code for the execute stage goes here. */ - - return decode_out; -} - -/** - * Memory stage implementation - */ -struct State memory_stage(struct State ex_out) { - - /* Your code for the memory stage goes here. */ - - return ex_out; -} - -/** - * Writeback stage implementation - */ -unsigned int write_back_stage(struct State mem_out) { - - /* Your code for the writeback stage goes here. */ - - return mem_out.inst; -} - -/** - * Advance PC. - * DO NOT MODIFY. - */ -void advance_pc(int step) { - pc_n += step; -} \ No newline at end of file diff --git a/pa2/src/sim_stages.h b/pa2/src/sim_stages.h deleted file mode 100644 index 4b3b88d..0000000 --- a/pa2/src/sim_stages.h +++ /dev/null @@ -1,26 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 2: Pipelined Simulator - * - * riscy-uconn: sim_stages.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -#include "sim_core.h" - -extern int debug; -extern int pipe_trace; - -unsigned int fetch(unsigned int instuction_fetch); -struct State decode(unsigned int instuction_fetch); -struct State execute(struct State decode_out); -struct State memory_stage(struct State alu_out); -unsigned int write_back_stage(struct State memory_out); -void advance_pc(int step); \ No newline at end of file diff --git a/pa2/src/util.c b/pa2/src/util.c deleted file mode 100644 index adee1a9..0000000 --- a/pa2/src/util.c +++ /dev/null @@ -1,211 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 2: Pipelined Simulator - * - * riscy-uconn: util.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include -#include -#include -#include -#include - -#include "instruction_map.h" -#include "register_map.h" -#include "sim_core.h" - -/** - * Dump register contents. - * Will format for desired number of columns and output in specified file. - */ -void rdump_file_columns(FILE* file, unsigned columns) { - static const unsigned int index_col_width = 4; - static const unsigned int name_col_width = 5; - static const unsigned int value_col_width = 8; - static const unsigned int tab_spaces = 4; - static const unsigned int col_sep = 2; - - assert(columns > 0); - - /* Calculate number of rows and total row length*/ - const unsigned int rows = (int)ceil((double) MAX_LENGTH / columns); - const unsigned int row_length = columns * (index_col_width + name_col_width + value_col_width + 2 + 2 * tab_spaces) + (columns - 1) * (col_sep * tab_spaces); - - /* Print header */ - fprintf(file, "---------------------\n"); - fprintf(file, "--- Register Dump ---\n"); - fprintf(file, "---------------------\n"); - for (int col = 0; col < columns; col++) { - fprintf(file, "%-*s%-*s%-*s", index_col_width + tab_spaces, "Index", name_col_width + tab_spaces, "Name", value_col_width + 2, "Value"); - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - for (int col = 0; col < columns; col++) { - fprintf(file, "%-*s%-*s%-*s", index_col_width + tab_spaces, "-----", name_col_width + tab_spaces, "----", value_col_width + 2, "-----"); - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - - /* Print rows */ - for (int row = 0; row < rows; row++) { - for (int col = 0; col < columns; col++) { - unsigned int i = row + col * rows; - - if (i < MAX_LENGTH) { - fprintf(file, "$%-*i%*s$%-*s%*s0x%0*x", index_col_width, i, tab_spaces - 1, "", name_col_width, register_map[i], tab_spaces - 1, "", value_col_width, registers[i]); - } else { - fprintf(file, "\n"); - break; - } - - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - } - fprintf(file, "%-*s%*s%-*s%*s0x%08x\n", index_col_width, "N/A", tab_spaces, "", name_col_width, "pc", tab_spaces, "", pc); -} - -void rdump_pt() { - rdump_file_columns(fptr_pt, 4); -} - -void rdump() { - rdump_file_columns(stdout, 4); -} - -/** - * Dump memory contents. - */ -void mdump() { - FILE* fptr; - fptr = fopen("mdump.txt", "w"); - int i = 0; - for (i = 0; i < 16384; i++) { - fprintf(fptr, "Memory[%d] = 0x%08x\n", i, memory[i]); - } - fclose(fptr); -} - -void inst_dump(const char stage[], const unsigned int inst) { - int opcode = inst >> 26; - - unsigned int func = inst << 26; - func = func >> 26; - - int rs = (inst >> 21) & 0x1F; - int rt = (inst >> 16) & 0x1F; - int rd = (inst >> 11) & 0x1F; - int sa = (inst >> 6) & 0x1F; - int imm = inst & 0xFFFF; - short shortImm = (short)imm; - int target = inst & 0x03ffffff; - - fprintf(fptr_pt, "%-12s ", stage); - - if (inst == 0xffffffff) { - fprintf(fptr_pt, "INVALID INSTRUCTION\n"); - return; - } - - switch (opcode) { - case RTYPEOP: - switch (func) { - case JR: - fprintf(fptr_pt, "%-4s %d\n", func_map[func], rs); - break; - - case SLL: - case SRL: - fprintf(fptr_pt, "%-4s $%d, $%d, %d\n", func_map[func], rd, rt, sa); - break; - - case ADD: - case SUB: - case AND: - case OR: - case SLT: - fprintf(fptr_pt, "%-4s $%d, $%d, $%d\n", func_map[func], rd, rs, rt); - break; - - default: - fprintf(fptr_pt, "INVALID INSTRUCTION\n"); - return; - break; - } - break; - - case LW: - case SW: - fprintf(fptr_pt, "%-4s $%d %d($%d)\n", opcode_map[opcode], rt, imm, rs); - break; - - case ANDI: - case ADDI: - case ORI: - case SLTI: - fprintf(fptr_pt, "%-4s $%d, $%d, %d\n", opcode_map[opcode], rt, rs, imm); - break; - - case LUI: - fprintf(fptr_pt, "%-4s $%d, %d\n", opcode_map[opcode], rt, imm); - break; - - case BEQ: - case BNE: - fprintf(fptr_pt, "%-4s $%d, $%d, %d\n", opcode_map[opcode], rs, rt, shortImm); - break; - - case J: - case JAL: - fprintf(fptr_pt, "%-4s %d", opcode_map[opcode], target); - break; - - default: - fprintf(fptr_pt, "INVALID INSTRUCTION\n"); - return; - break; - } -} - -// Convert a binary string to a decimal value -int getDec(char *bin) { - int b, k, m, n; - int len, sum = 0; - - // Length - 1 to accomodate for null terminator - len = strlen(bin) - 1; - - // Iterate the string - for (k = 0; k <= len; k++) { - // Convert char to numeric value - n = (bin[k] - '0'); - - // Check the character is binary - if ((n > 1) || (n < 0)) { - return 0; - } - - for (b = 1, m = len; m > k; m--) - b *= 2; - - // sum it up - sum = sum + n * b; - } - return sum; -} \ No newline at end of file diff --git a/pa2/src/util.h b/pa2/src/util.h deleted file mode 100644 index 22e8df9..0000000 --- a/pa2/src/util.h +++ /dev/null @@ -1,23 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 2: Pipelined Simulator - * - * riscy-uconn: util.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -#include - -void rdump_file_columns(FILE* file, unsigned columns); -void rdump(); -void rdump_pt(); -void mdump(); -void inst_dump(const char stage[], const unsigned int inst); -int getDec(char *bin); \ No newline at end of file diff --git a/pa2/unittests/.gitignore b/pa2/unittests/.gitignore deleted file mode 100644 index e2e7327..0000000 --- a/pa2/unittests/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/out diff --git a/pa2/unittests/array_adder.asm b/pa2/unittests/array_adder.asm deleted file mode 100644 index f4bf43d..0000000 --- a/pa2/unittests/array_adder.asm +++ /dev/null @@ -1,59 +0,0 @@ -.text -addi $t9, $zero, 10 -loop: -lw $t2, 2049($t1) #t2 = mem[2049 + t1] -lw $t3, 2065($t1) #t3 = mem[2065 + t1] -addi $t1, $t1, 1 #t1++ -lw $t4, 2049($t1) #t4 = mem[2049 + t1] -lw $t5, 2065($t1) #t5 = mem[2065 + t1] -addi $t1, $t1, 1 #t1++ - -add $t6, $t2, $t3 #t6 = 20, 60, 100, 140, 180 -add $t7, $t4, $t5 #t7 = 40, 80, 120, 160, 200 - -sw $t6, 2048($t8) -addi $t8, $t8, 1 -sw $t7, 2048($t8) -addi $t8, $t8, 1 - -bne $t1, $t9, loop - -addi $zero, $zero, 1 - - -.data -2048: .word 10 -2049: .word 10 -2050: .word 20 -2051: .word 30 -2052: .word 40 -2053: .word 50 -2054: .word 60 -2055: .word 70 -2056: .word 80 -2057: .word 90 -2058: .word 100 -2059: .word 3 -2060: .word 3 -2061: .word 3 -2062: .word 3 -2063: .word -2064: .word 11 -2065: .word 10 -2066: .word 20 -2067: .word 30 -2068: .word 40 -2069: .word 50 -2070: .word 60 -2071: .word 70 -2072: .word 80 -2073: .word 90 -2074: .word 100 -2075: .word 3 -2076: .word 3 -2077: .word 3 -2078: .word 3 -2079: .word 3 -2080: .word 5 - - diff --git a/pa2/unittests/beq_no_dep.asm b/pa2/unittests/beq_no_dep.asm deleted file mode 100644 index 894c249..0000000 --- a/pa2/unittests/beq_no_dep.asm +++ /dev/null @@ -1,22 +0,0 @@ -.text -addi $t0, $zero, 10 -addi $t1, $zero, 10 -addi $t2, $zero, 20 -addi $t3, $zero, 21 -addi $t4, $zero, 22 -addi $t5, $zero, 23 -beq $t0, $t1, loop -sw $t0, 2048($zero) -sw $t1, 2049($zero) -sw $t2, 2050($zero) -addi $t0, $zero, 30 - -loop: -lw $t0, 2048($zero) -addi, $zero, $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 5119 -2049: .word 32 - - diff --git a/pa2/unittests/fibonacci.asm b/pa2/unittests/fibonacci.asm deleted file mode 100644 index f086574..0000000 --- a/pa2/unittests/fibonacci.asm +++ /dev/null @@ -1,50 +0,0 @@ -.text -addi $t9, $zero, 10 -addi $t1, $zero, 0 -addi $t2, $zero, 1 -j fibonacci - -fibonacci: -add $t3, $t2, $t1 -add $t1, $zero, $t2 -add $t2, $zero, $t3 -addi $t5, $t5, 1 -bne $t5, $t9, fibonacci -addi $zero $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 10 -2049: .word 10 -2050: .word 20 -2051: .word 30 -2052: .word 40 -2053: .word 50 -2054: .word 60 -2055: .word 70 -2056: .word 80 -2057: .word 90 -2058: .word 100 -2059: .word 3 -2060: .word 3 -2061: .word 3 -2062: .word 3 -2063: .word -2064: .word 11 -2065: .word 10 -2066: .word 20 -2067: .word 30 -2068: .word 40 -2069: .word 50 -2070: .word 60 -2071: .word 70 -2072: .word 80 -2073: .word 90 -2074: .word 100 -2075: .word 3 -2076: .word 3 -2077: .word 3 -2078: .word 3 -2079: .word 3 -2080: .word 5 - - diff --git a/pa2/unittests/j_no_dep_test1.asm b/pa2/unittests/j_no_dep_test1.asm deleted file mode 100644 index 16aaf13..0000000 --- a/pa2/unittests/j_no_dep_test1.asm +++ /dev/null @@ -1,24 +0,0 @@ -.text -add $t0, $zero, $zero # iterator i = 0 -addi $t2, $zero, 1 # init t2 = 1 -add $t3, $zero, $zero # initialize temporary register to zero -add $t4, $zero, $zero # initialize temporary register to zero -j jump_test1 # Jump to procedure "jump_test1" - -jump_test2: -lw $a1, 2048($t0) # Load a1 = 2, Mem[2048] = 2, 2 in simulator -lw $a2, 2048($t2) # Load a2 = 10, Mem[2049] = 10, 10 in simulator -j end # Jump to procedure "end" - -jump_test1: -add $t5, $zero, $zero # initialize temporary register to zero -add $t6, $zero, $zero # initialize temporary register to zero -j jump_test2 # Jump to procedure "jump_test2" - -end: -addi, $zero, $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 2 -2049: .word 10 - diff --git a/pa2/unittests/jal_test1.asm b/pa2/unittests/jal_test1.asm deleted file mode 100644 index 6e7131d..0000000 --- a/pa2/unittests/jal_test1.asm +++ /dev/null @@ -1,23 +0,0 @@ -.text -addi $a0, $zero, 2 # argument 0 = 2 -addi $a1, $zero, 3 # argument 1 = 3 -addi $a2, $zero, 4 # argument 2 = 4 -addi $a3, $zero, 5 # argument 3 = 5 -add $t4, $zero, $zero -jal diffofsums # call procedure -addi, $zero, $zero, 1 # $zero register should never be updated, so detect this change and quit simulator -sll $zero, $zero, 1 # -sll $zero, $zero, 1 # - - - -diffofsums: -add $t0, $a0, $a1 # $t0 = f + g -add $t1, $a2, $a3 # $t1 = h + i -sub $s0, $t0, $t1 # result = (f+g)-(h+i) -add $v0, $s0, $zero # put return value in $v0 -jr $ra # return to caller - -.data -2048: .word 10 -2049: .word 10 diff --git a/pa2/unittests/lw_sw_test1.asm b/pa2/unittests/lw_sw_test1.asm deleted file mode 100644 index 2811d0c..0000000 --- a/pa2/unittests/lw_sw_test1.asm +++ /dev/null @@ -1,59 +0,0 @@ -.text -add $t0, $zero, $zero # i = 0 -add $t1, $zero, $zero # initialize the sum to zero -add $t2, $zero, $zero # for second loop compare 2 -add $t3, $zero, $zero -add $t5, $zero, $zero # initialize temporary register to zero -add $t6, $zero, $zero # for sw later -add $t7, $zero, $zero - -lw $t1, 2048($t0) # $t1=20 -lw $t2, 2048($t1) # $t2=4 -add $t4, $t1, $t2 # $t4=24 -lw $t3, 2048($t4) # $t3=8 -add $t4, $t4, $t3 # $t4=32 -sw $t4, 2048($t0) # mem[2048]=32 -lw $t1, 2048($t0) # $t1=32 <-- observation of stored value 32 as $t1=0x00000020 -lw $t2, 2048($t1) # $t2=5 -add $t4, $t1, $t2 # $t4=37 -sw $t4, 2048($t1) # mem[2080]=37 -lw $t5, 2048($t1) # $t5=37 <--- observation of stored value 37 as $t5=0x00000025 -addi, $zero, $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - - -.data -2048: .word 20 -2049: .word 32 -2050: .word 2 -2051: .word 2 -2052: .word 3 -2053: .word 3 -2054: .word 3 -2055: .word 3 -2056: .word 3 -2057: .word 3 -2058: .word 3 -2059: .word 3 -2060: .word 3 -2061: .word 3 -2062: .word 3 -2063: .word 3 -2064: .word 3 -2065: .word 3 -2066: .word 3 -2067: .word 3 -2068: .word 4 -2069: .word 3 -2070: .word 3 -2071: .word 3 -2072: .word 8 -2073: .word 3 -2074: .word 3 -2075: .word 3 -2076: .word 3 -2077: .word 3 -2078: .word 3 -2079: .word 3 -2080: .word 5 - - diff --git a/pa2/unittests/lw_sw_test2.asm b/pa2/unittests/lw_sw_test2.asm deleted file mode 100644 index a266623..0000000 --- a/pa2/unittests/lw_sw_test2.asm +++ /dev/null @@ -1,60 +0,0 @@ -.text -add $t0, $zero, $zero # i = 0 -add $t1, $zero, $zero # initialize the sum to zero -add $t2, $zero, $zero # for second loop compare 2 -add $t3, $zero, $zero -add $t5, $zero, $zero # initialize temporary register to zero -add $t6, $zero, $zero # for sw later -add $t7, $zero, $zero - -lw $t1, 2048($t0) # $t1=20 -add $t4, $t1, $t1 # $t4=40 -lw $t3, 2048($t4) # $t3=57 -addi, $zero, $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - - -.data -2048: .word 20 -2049: .word 32 -2050: .word 2 -2051: .word 2 -2052: .word 3 -2053: .word 3 -2054: .word 3 -2055: .word 3 -2056: .word 3 -2057: .word 3 -2058: .word 3 -2059: .word 3 -2060: .word 3 -2061: .word 3 -2062: .word 3 -2063: .word 3 -2064: .word 3 -2065: .word 3 -2066: .word 3 -2067: .word 3 -2068: .word 4 -2069: .word 3 -2070: .word 3 -2071: .word 3 -2072: .word 8 -2073: .word 3 -2074: .word 3 -2075: .word 3 -2076: .word 3 -2077: .word 3 -2078: .word 3 -2079: .word 3 -2080: .word 5 -2081: .word 50 -2082: .word 51 -2083: .word 52 -2084: .word 53 -2085: .word 54 -2086: .word 55 -2087: .word 56 -2088: .word 57 - - - diff --git a/pa2/unittests/no_dep_test1.asm b/pa2/unittests/no_dep_test1.asm deleted file mode 100644 index 619e23a..0000000 --- a/pa2/unittests/no_dep_test1.asm +++ /dev/null @@ -1,14 +0,0 @@ -.text -addi $t0, $zero, 10 -addi $t1, $zero, 25 -addi $t2, $zero, 20 -addi $t3, $zero, 19 -addi $t4, $zero, 18 -sw $t0, 2048($zero) -addi, $zero, $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 5119 -2049: .word 32 - - diff --git a/pa3/Makefile b/pa3/Makefile deleted file mode 100644 index b17f6b5..0000000 --- a/pa3/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -SRCS = $(wildcard src/*.c) -HEADERS = $(wildcard src/*.h) -CC = gcc -CFLAGS = -g -std=c99 -LDFLAGS = -lm - -default: simulator - -simulator: $(SRCS) $(HEADERS) - @echo "Building $@..." - @echo "Sources: $(SRCS)" - @echo "Headers: $(HEADERS)" - $(CC) $(CFLAGS) -o $@ $(SRCS) $(LDFLAGS) - -clean: - -rm -f simulator - -rm -f pipe_trace.txt *.out mdump.txt cdump.txt diff --git a/pa3/README.md b/pa3/README.md deleted file mode 100644 index 28ad64d..0000000 --- a/pa3/README.md +++ /dev/null @@ -1,27 +0,0 @@ -# Programming Assignment 3: Pipelined riscy-uconn Simulator with Multi-cycle Operations and Data Cache - -A 5-stage pipelined CPU simulator with multi-cycle operations and data cache for the MIPS-like -riscy-uconn instruction set architecture. The simulator translates machine code created by the -riscy-uconn assembler, and executes instructions one at a time. Each instruction goes through a -Fetch, Decode, Execute, Memory and Writeback stage of processing. - -## Build Instructions - $ make - -## Usage - $ ./simulator assembled_program_file.out FORWARDING_ENABLED DATA_CACHE_ENABLED - -where `assembled_program_file.out` may be any assembled program file generated by the riscy-uconn -assembler, `FORWARDING_ENABLED` may be 0 (disabled) or 1 (enabled), and `DATA_CACHE_ENABLED` may be -0 (disabled) or 1 (enabled). - -## Unit Tests -Several unit tests are provided in the `unittests` directory. These unit tests must be assembled -before use with the simulator by executing the following command: - - $ ../assembler/assembler unittests/unit_test_file.asm unittests/unit_test_file.out - -where `unit_test_file` is any of the unit test files (written in riscy-uconn assembly) in the -`unittests` directory. - - diff --git a/pa3/src/instruction_map.c b/pa3/src/instruction_map.c deleted file mode 100644 index f29ac4a..0000000 --- a/pa3/src/instruction_map.c +++ /dev/null @@ -1,40 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache - * - * riscy-uconn: instruction_map.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include "instruction_map.h" - -char* opcode_map[] = { - [RTYPEOP] = "RTYPEOP", - [LW] = "lw", - [SW] = "sw", - [ANDI] = "andi", - [ADDI] = "addi", - [ORI] = "ori", - [SLTI] = "slti", - [LUI] = "lui", - [BEQ] = "beq", - [BNE] = "bne", - [J] = "j", - [JAL] = "jal" -}; - -char* func_map[] = { - [ADD] = "add", - [SUB] = "sub", - [AND] = "and", - [OR] = "or", - [SLL] = "sll", - [SRL] = "srl", - [SLT] = "slt", - [JR] = "jr" -}; \ No newline at end of file diff --git a/pa3/src/instruction_map.h b/pa3/src/instruction_map.h deleted file mode 100644 index 3401e4e..0000000 --- a/pa3/src/instruction_map.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache - * - * riscy-uconn: instruction_map.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -extern char* opcode_map[]; -extern char* func_map[]; - -/* R-Type Instructions */ -#define RTYPEOP 0x0 -#define ADD 0x20 -#define SUB 0x21 -#define AND 0x24 -#define OR 0x25 -#define SLL 0x0 -#define SLT 0x2A -#define SRL 0x2 -#define JR 0x8 - -/* I-Type Instructions */ -#define LW 0x23 -#define SW 0x2B -#define ANDI 0xC -#define ORI 0xD -#define LUI 0xF -#define BEQ 0x4 -#define BNE 0x5 -#define SLTI 0xA -#define ADDI 0x8 - -/* J-Type Instructions */ -#define J 0x2 -#define JAL 0x3 \ No newline at end of file diff --git a/pa3/src/register_map.c b/pa3/src/register_map.c deleted file mode 100644 index 94025e9..0000000 --- a/pa3/src/register_map.c +++ /dev/null @@ -1,49 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache - * - * riscy-uconn: register_map.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include "register_map.h" - -const char* register_map[] = { - [0] = "zero", - [1] = "at", - [2] = "v0", - [3] = "v1", - [4] = "a0", - [5] = "a1", - [6] = "a2", - [7] = "a3", - [8] = "t0", - [9] = "t1", - [10] = "t2", - [11] = "t3", - [12] = "t4", - [13] = "t5", - [14] = "t6", - [15] = "t7", - [16] = "s0", - [17] = "s1", - [18] = "s2", - [19] = "s3", - [20] = "s4", - [21] = "s5", - [22] = "s6", - [23] = "s7", - [24] = "t8", - [25] = "t9", - [26] = "k0", - [27] = "k1", - [28] = "gp", - [29] = "sp", - [30] = "fp", - [31] = "ra", -}; \ No newline at end of file diff --git a/pa3/src/register_map.h b/pa3/src/register_map.h deleted file mode 100644 index d8a7e1b..0000000 --- a/pa3/src/register_map.h +++ /dev/null @@ -1,16 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache - * - * riscy-uconn: register_map.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -extern const char* register_map[]; \ No newline at end of file diff --git a/pa3/src/sim_core.c b/pa3/src/sim_core.c deleted file mode 100644 index b3d73d7..0000000 --- a/pa3/src/sim_core.c +++ /dev/null @@ -1,290 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache - * - * riscy-uconn: sim_core.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include -#include -#include - -#include "instruction_map.h" -#include "register_map.h" -#include "sim_core.h" -#include "sim_stages.h" -#include "util.h" - -/** - * Initial CPU state - */ -int cycle = 0; // CPU cycle -int registers[MAX_LENGTH] = {0}; // Registers -unsigned int pc = 0; // Program Counter (PC) register -unsigned int pc_n = 0; -int *memory = NULL; // Data & instruction memory - -/* Pipeline-related initialization */ -int forwarding_enabled = 0; -int pipe_stall = 0; -int br_taken = 0; -int lw_in_exe = 0; -int we_exe = 0, ws_exe = 0, dout_exe = 0; -int we_mem = 0, ws_mem = 0, dout_mem = 0; -int we_wb = 0, ws_wb = 0, dout_wb = 0; - -/* Multi-cycle operation-related initialization */ -const int dmem_access_cycles = 10; -const int rtype_execute_cycles = 5; -int dmem_busy = 0; -int dmem_cycles = 0; -int exe_busy = 0; -int exe_cycles = 0; - -/* Data cache-related */ -int dcache_enabled = 0; -int dcache_accesses = 0; -int dcache_hits = 0; - -/** - * Utility - */ -FILE *fptr_pt; - -/** - * Simulator entry point - */ -int main(int argc, char *argv[]) { - if (argc != 4) { - fprintf(stderr, "[ERROR] incorrect number of arguments.\n"); - printf("usage: simulator PROGRAM_FILE FORWARDING_ENABLED DATA_CACHE_ENABLED\n"); - exit(1); - } else { - /* Open input program file */ - FILE *fp; - fp = fopen(argv[1], "r"); - - /* Enable/disable forwarding */ - sscanf(argv[2],"%d", &forwarding_enabled); - if (forwarding_enabled > 1) { - fprintf(stderr, "[ERROR] FORWARDING_ENABLED must be either 0 (disabled) or 1 (enabled).\n"); - exit(1); - } - printf("Pipeline Forwarding: %s\n", forwarding_enabled ? "Enabled" : "Disabled"); - - /* Enable/disable data cache */ - sscanf(argv[3], "%d", &dcache_enabled); - if (dcache_enabled > 1) { - fprintf(stderr, "[ERROR] DATA_CACHE_ENABLED must be either 0 (disabled) or 1 (enabled).\n"); - exit(1); - } - printf("Data Cache: %s\n", dcache_enabled ? "Enabled" : "Disabled"); - - /* Open pipe trace */ - if (pipe_trace) { - fptr_pt = fopen("pipe_trace.txt", "w"); - } - - /* Initialize registers and instruction/data memory */ - initialize(fp); - - puts("\n"); - printf("Simulating...\n"); - - /* Process instructions one at a time */ - process_instructions(); - - puts(""); - - /* Output state after termination */ - rdump(); // Register dump - mdump(); // Memory dump - cdump(); // Cache dump - printf("\nData Cache Accesses = %d\nData Cache Hits = %d\n", dcache_accesses, dcache_hits); - - /* Cleanup */ - free(memory); - free(dcache); - fclose(fp); - if (pipe_trace) { - fclose(fptr_pt); - } - - return 0; - } -} - -void process_instructions() { - int terminate = 0; - int instruction_counter = 0; //committed instruction count - - /* Initialize pipeline state */ - unsigned int committed_inst; - fetch_out = 0; - decode_out = (struct State) {0}; - ex_out = (struct State) {0}; - mem_out = (struct State) {0}; - - while (terminate != 1) { - /* Update pipeline state */ - committed_inst = write_back_stage(mem_out); - mem_out_n = memory_stage(ex_out); - ex_out_n = execute(decode_out); - decode_out_n = decode(fetch_out); - fetch_out_n = fetch(fetch_out); - - if (pipe_trace == 1) { - fprintf(fptr_pt, "Cycle %d, PC %d, Next PC %d\n", cycle, pc, pc_n); - inst_dump("[Fetch]", fetch_out_n); - inst_dump("[Decode]", decode_out_n.inst); - inst_dump("[Execute]", ex_out_n.inst); - inst_dump("[Memory]", mem_out_n.inst); - inst_dump("[Writeback]", committed_inst); - fprintf(fptr_pt, "\n"); - rdump_pt(); - fprintf(fptr_pt, "\n"); - fprintf(fptr_pt, "=================================================================================================================================\n"); - fprintf(fptr_pt, "\n"); - } - - if (debug) { - fprintf(stderr, "[DEBUG] Cycle: %d, Instruction Memory Address: %d, Instruction: 0x%08x\n", cycle, pc / 4, fetch_out_n); - } - - if ((committed_inst != 0xffffffff) & (committed_inst != 0x00000000)) { - instruction_counter++; - } - - if (debug) { - fprintf(stderr, "[DEBUG] Cycle: %d, Committed Instruction: 0x%08x\n", cycle, committed_inst); - } - - if (registers[0] != 0) { - terminate = 1; // set terminate flag when $zero is updated - } - - /* Update state for next cycle */ - update_simulator_state(); - cycle++; - - /* Potential infinite loop detected */ - if (cycle == 10000) { - fprintf(stderr, "\n[WARNING] Simulation has simulated 10,000 cycles without terminating. Something might be wrong. Press CTRL + C to force termination.\n"); - } - - /* Flush pipe trace to file */ - if (pipe_trace) { - fflush(fptr_pt); - } - } - printf("\nFinished simulation!\n"); - printf("\nTOTAL INSTRUCTIONS COMMITTED: %d\n", instruction_counter); - printf("TOTAL CYCLES SIMULATED: %d\n", cycle); -} - -void initialize(FILE *fp) { - printf("======================================\n"); - printf("=== BEGIN SIMULATOR INITIALIZATION ===\n"); - printf("======================================\n"); - if (fp == NULL) { - fprintf(stderr, "[ERROR] opening input file. Aborting.\n"); - exit(1); - } - - /* Zero initialize registers */ - memset(registers, 0, sizeof(registers)); - printf("Initialized Registers\n"); - - /* Allocate and zero-initialize data cache */ - dcache = (CacheBlock*) calloc(NUM_DCACHE_LINES, sizeof(CacheBlock)); - if (dcache == NULL) { - fprintf(stderr, "[ERROR] not enough memory. Aborting.\n"); - exit(1); - } - printf("Initialized Data Cache\n"); - - /* Allocate instruction and data memory */ - memory = (int*) malloc(16384 * sizeof(int)); - if (memory == NULL) { - fprintf(stderr, "[ERROR] not enough memory. Aborting.\n"); - exit(1); - } - - /* Initialize memory to -1 */ - for (int i = 0; i < 16384; i++) { - memory[i] = -1; - } - printf("Initialized Memory\n"); - puts(""); - - printf("----------------------\n"); - printf("--- Section: .text ---\n"); - printf("----------------------\n"); - - /* Initialize parsing variables */ - char line[MAX_LENGTH + 2]; - char *p; - int i = 0, line_num = 0; - - /* Copy .text section to memory, break at nop */ - while (fgets(line, MAX_LENGTH + 2, fp) != NULL) { - line_num++; - - /* Remove '\n' from 'line' */ - p = strchr(line, '\n'); - if (p != NULL) { - *p = '\0'; - } - - memory[i] = getDec(line); - - /* If 'nop' found, move to 0x800 / 2048 in memory and break */ - if (strcmp(line, "11111111111111111111111111111111") == 0) { - memory[i] = 0; - i = 0x800; - break; - } else { - printf("memory[%d] = 0x%08x\n", i, memory[i]); - i++; - } - } - - int j = 2048; //Data Memory Starts at 2048 - for (j = i; j < 16384; j++) { - memory[j] = 0; - } - - puts(""); - - printf("----------------------\n"); - printf("--- Section: .data ---\n"); - printf("----------------------\n"); - - /* Seek fp to first instruction in .data */ - char data[MAX_LENGTH + 2]; - int bytes = 33 * line_num; - fseek(fp, bytes, SEEK_SET); - - /* Copy .data section to memory */ - while (fgets(line, MAX_LENGTH + 2, fp) != NULL) { - /* Remove '\n' from 'line' */ - p = strchr(line, '\n'); - if (p != NULL) { - *p = '\0'; - } - - memory[i] = getDec(line); - printf("memory[%d] = 0x%08x\n", i, memory[i]); - i++; - } - - printf("====================================\n"); - printf("=== END SIMULATOR INITIALIZATION ===\n"); - printf("===================================="); -} diff --git a/pa3/src/sim_core.h b/pa3/src/sim_core.h deleted file mode 100644 index 4a87ce6..0000000 --- a/pa3/src/sim_core.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache - * - * riscy-uconn: sim_core.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -#include - -extern FILE *fptr_pt; - -/* Max number of registers, and instruction length in bits */ -#define MAX_LENGTH 32 - -/* Array of registers (register file) */ -extern int registers[MAX_LENGTH]; - -/* Clock cycle */ -extern int cycle; - -/* Program Counter (PC) register */ -extern unsigned int pc; // Current PC -extern unsigned int pc_n; // Next PC - -/* Microarchitectural state */ -unsigned int fetch_out, fetch_out_n; -struct State decode_out, decode_out_n; -struct State ex_out, ex_out_n; -struct State mem_out, mem_out_n; - -/* Instruction and data memory */ -extern int *memory; - -/* CPU state */ -struct State { - /* Fetched instruction */ - unsigned int inst; - - /* Decoded instruction fields */ - unsigned int opcode; - unsigned int func; - unsigned int rs; - unsigned int rt; - unsigned int rd; - unsigned int sa; - unsigned short imm; - - /* Memory related */ - unsigned int mem_flag; - unsigned int mem_addr; - unsigned int mem_out; - - /* JAL related */ - unsigned int jmp_out_31; - - /* ALU */ - unsigned int alu_in1; - unsigned int alu_in2; - unsigned int alu_out; -}; - -/* Pipeline-related */ -extern int forwarding_enabled; -extern int pipe_stall; -extern int br_taken; -extern int lw_in_exe; -extern int we_exe, ws_exe, dout_exe; -extern int we_mem, ws_mem, dout_mem; -extern int we_wb, ws_wb, dout_wb; - -/* Multi-cycle operation-related */ -extern const int dmem_access_cycles; -extern const int rtype_execute_cycles; -extern int dmem_busy; -extern int dmem_cycles; -extern int exe_busy; -extern int exe_cycles; - -/* Data cache-related */ -extern int dcache_enabled; -extern int dcache_accesses; -extern int dcache_hits; - -#define NUM_DCACHE_LINES 32 // 1024 bytes (cache size) / 32 bytes (block size) - -typedef struct { - int valid; - int tag; -} CacheBlock; - -CacheBlock *dcache; - -void initialize(FILE *fp); -void process_instructions(); \ No newline at end of file diff --git a/pa3/src/sim_stages.c b/pa3/src/sim_stages.c deleted file mode 100644 index ba94057..0000000 --- a/pa3/src/sim_stages.c +++ /dev/null @@ -1,127 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * YOUR NAME HERE - * - * Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache - * - * riscy-uconn: sim_stages.c - * - */ - -#include -#include -#include - -#include "instruction_map.h" -#include "sim_core.h" -#include "sim_stages.h" - -/** - * Debug flags - */ -int debug = 0; // Set to 1 for additional debugging information. -int pipe_trace = 1; // Set to 1 for pipe trace. - -/** - * Fetch stage implementation. - */ -unsigned int fetch(unsigned int fetch_in) { - unsigned int inst = 0; - - /* Your code for the fetch stage goes here. */ - - return inst; -} - -/** - * Decode stage implementation - */ -struct State decode(unsigned int fetch_out) { - struct State decode_out = {0}; - - /* Your code for the decode stage goes here. */ - - return decode_out; -} - -/** - * Execute stage implementation - */ -struct State execute(struct State decode_out) { - - /* Your code for the execute stage goes here. */ - - return decode_out; -} - -/** - * Memory stage implementation - */ -struct State memory_stage(struct State ex_out) { - - /* Your code for the memory stage goes here. */ - - return ex_out; -} - -/** - * Write-back stage implementation - */ -unsigned int write_back_stage(struct State mem_out) { - - /* Your code for the write-back stage goes here. */ - - return mem_out.inst; -} - -/** - * Update simulator state for next cycle - */ -void update_simulator_state() { - if (dmem_busy == 1) { - - /* Your code to hold fetch, decode, execute, and memory stages goes here. */ - - } else if (exe_busy == 1) { - - /* Your code to hold fetch, decode, and execute stages goes here. */ - - } else { - /* DO NOT MODIFY. */ - pc = pc_n; - fetch_out = fetch_out_n; - decode_out = decode_out_n; - ex_out = ex_out_n; - mem_out = mem_out_n; - } -} - -/** - * Data cache lookup - */ -int dcache_lookup(int addr_mem) { - int hit = 0; - - /* Your code for data cache lookup goes here. */ - - return hit; -} - -/** - * Data cache update - */ -void dcache_update(int addr_mem) { - - /* Your code for data cache update logic goes here. */ - -} - -/** - * Advance PC. - * DO NOT MODIFY. - */ -void advance_pc(int step) { - pc_n += step; -} \ No newline at end of file diff --git a/pa3/src/sim_stages.h b/pa3/src/sim_stages.h deleted file mode 100644 index 360164f..0000000 --- a/pa3/src/sim_stages.h +++ /dev/null @@ -1,29 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache - * - * riscy-uconn: sim_stages.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -#include "sim_core.h" - -extern int debug; -extern int pipe_trace; - -unsigned int fetch(unsigned int instuction_fetch); -struct State decode(unsigned int instuction_fetch); -struct State execute(struct State decode_out); -struct State memory_stage(struct State alu_out); -unsigned int write_back_stage(struct State memory_out); -void update_simulator_state(); -int dcache_lookup(int addr_mem); -void dcache_update(int addr_mem); -void advance_pc(int step); \ No newline at end of file diff --git a/pa3/src/util.c b/pa3/src/util.c deleted file mode 100644 index 0f57b1a..0000000 --- a/pa3/src/util.c +++ /dev/null @@ -1,227 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache - * - * riscy-uconn: util.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include -#include -#include -#include -#include - -#include "instruction_map.h" -#include "register_map.h" -#include "sim_core.h" - -/** - * Dump register contents. - * Will format for desired number of columns and output in specified file. - */ -void rdump_file_columns(FILE* file, unsigned columns) { - static const unsigned int index_col_width = 4; - static const unsigned int name_col_width = 5; - static const unsigned int value_col_width = 8; - static const unsigned int tab_spaces = 4; - static const unsigned int col_sep = 2; - - assert(columns > 0); - - /* Calculate number of rows and total row length*/ - const unsigned int rows = (int)ceil((double) MAX_LENGTH / columns); - const unsigned int row_length = columns * (index_col_width + name_col_width + value_col_width + 2 + 2 * tab_spaces) + (columns - 1) * (col_sep * tab_spaces); - - /* Print header */ - fprintf(file, "---------------------\n"); - fprintf(file, "--- Register Dump ---\n"); - fprintf(file, "---------------------\n"); - for (int col = 0; col < columns; col++) { - fprintf(file, "%-*s%-*s%-*s", index_col_width + tab_spaces, "Index", name_col_width + tab_spaces, "Name", value_col_width + 2, "Value"); - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - for (int col = 0; col < columns; col++) { - fprintf(file, "%-*s%-*s%-*s", index_col_width + tab_spaces, "-----", name_col_width + tab_spaces, "----", value_col_width + 2, "-----"); - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - - /* Print rows */ - for (int row = 0; row < rows; row++) { - for (int col = 0; col < columns; col++) { - unsigned int i = row + col * rows; - - if (i < MAX_LENGTH) { - fprintf(file, "$%-*i%*s$%-*s%*s0x%0*x", index_col_width, i, tab_spaces - 1, "", name_col_width, register_map[i], tab_spaces - 1, "", value_col_width, registers[i]); - } else { - fprintf(file, "\n"); - break; - } - - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - } - fprintf(file, "%-*s%*s%-*s%*s0x%08x\n", index_col_width, "N/A", tab_spaces, "", name_col_width, "pc", tab_spaces, "", pc); -} - -void rdump_pt() { - rdump_file_columns(fptr_pt, 4); -} - -void rdump() { - rdump_file_columns(stdout, 4); -} - -/** - * Dump memory contents. - */ -void mdump() { - FILE* fptr; - fptr = fopen("mdump.txt", "w"); - int i = 0; - for (i = 0; i < 16384; i++) { - fprintf(fptr, "Memory[%d] = 0x%08x\n", i, memory[i]); - } - fclose(fptr); -} - -/** - * Dump cache information - */ -void cdump() { - FILE *fptr; - fptr = fopen("cdump.txt","w"); - - for (int i = 0; i < NUM_DCACHE_LINES; i++){ - fprintf(fptr,"DataCache[%d].valid = %d, DataCache[%d].tag = %d\n", i, dcache[i].valid, i, dcache[i].tag); - } -} - -/** - * Print instruction information - */ -void inst_dump(const char stage[], const unsigned int inst) { - int opcode = inst >> 26; - - unsigned int func = inst << 26; - func = func >> 26; - - int rs = (inst >> 21) & 0x1F; - int rt = (inst >> 16) & 0x1F; - int rd = (inst >> 11) & 0x1F; - int sa = (inst >> 6) & 0x1F; - int imm = inst & 0xFFFF; - short shortImm = (short)imm; - int target = inst & 0x03ffffff; - - fprintf(fptr_pt, "%-12s ", stage); - - if (inst == 0xffffffff) { - fprintf(fptr_pt, "INVALID INSTRUCTION\n"); - return; - } - - switch (opcode) { - case RTYPEOP: - switch (func) { - case JR: - fprintf(fptr_pt, "%-4s $%d\n", func_map[func], rs); - break; - - case SLL: - case SRL: - fprintf(fptr_pt, "%-4s $%d, $%d, %d\n", func_map[func], rd, rt, sa); - break; - - case ADD: - case SUB: - case AND: - case OR: - case SLT: - fprintf(fptr_pt, "%-4s $%d, $%d, $%d\n", func_map[func], rd, rs, rt); - break; - - default: - fprintf(fptr_pt, "INVALID INSTRUCTION\n"); - return; - break; - } - break; - - case LW: - case SW: - fprintf(fptr_pt, "%-4s $%d %d($%d)\n", opcode_map[opcode], rt, imm, rs); - break; - - case ANDI: - case ADDI: - case ORI: - case SLTI: - fprintf(fptr_pt, "%-4s $%d, $%d, %d\n", opcode_map[opcode], rt, rs, imm); - break; - - case LUI: - fprintf(fptr_pt, "%-4s $%d, %d\n", opcode_map[opcode], rt, imm); - break; - - case BEQ: - case BNE: - fprintf(fptr_pt, "%-4s $%d, $%d, %d\n", opcode_map[opcode], rs, rt, shortImm); - break; - - case J: - case JAL: - fprintf(fptr_pt, "%-4s %d\n", opcode_map[opcode], target); - break; - - default: - fprintf(fptr_pt, "INVALID INSTRUCTION\n"); - return; - break; - } -} - -/** - * Convert a binary string to an integer - */ -int getDec(char *bin) { - int b, k, m, n; - int len, sum = 0; - - len = strlen(bin) - 1; - - /* Iterate over the string */ - for (k = 0; k <= len; k++) { - // Convert char to numeric value - n = (bin[k] - '0'); - - // Check the character is binary - if ((n > 1) || (n < 0)) { - return 0; - } - - for (b = 1, m = len; m > k; m--) - b *= 2; - - // sum it up - sum = sum + n * b; - } - return sum; -} \ No newline at end of file diff --git a/pa3/src/util.h b/pa3/src/util.h deleted file mode 100644 index 83a3b2d..0000000 --- a/pa3/src/util.h +++ /dev/null @@ -1,24 +0,0 @@ -/** - * University of Connecticut - * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache - * - * riscy-uconn: util.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -#include - -void rdump_file_columns(FILE* file, unsigned columns); -void rdump(); -void rdump_pt(); -void mdump(); -void cdump(); -void inst_dump(const char stage[], const unsigned int inst); -int getDec(char *bin); \ No newline at end of file diff --git a/pa3/unittests/.gitignore b/pa3/unittests/.gitignore deleted file mode 100644 index e2e7327..0000000 --- a/pa3/unittests/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/out diff --git a/pa3/unittests/array_adder.asm b/pa3/unittests/array_adder.asm deleted file mode 100644 index f4bf43d..0000000 --- a/pa3/unittests/array_adder.asm +++ /dev/null @@ -1,59 +0,0 @@ -.text -addi $t9, $zero, 10 -loop: -lw $t2, 2049($t1) #t2 = mem[2049 + t1] -lw $t3, 2065($t1) #t3 = mem[2065 + t1] -addi $t1, $t1, 1 #t1++ -lw $t4, 2049($t1) #t4 = mem[2049 + t1] -lw $t5, 2065($t1) #t5 = mem[2065 + t1] -addi $t1, $t1, 1 #t1++ - -add $t6, $t2, $t3 #t6 = 20, 60, 100, 140, 180 -add $t7, $t4, $t5 #t7 = 40, 80, 120, 160, 200 - -sw $t6, 2048($t8) -addi $t8, $t8, 1 -sw $t7, 2048($t8) -addi $t8, $t8, 1 - -bne $t1, $t9, loop - -addi $zero, $zero, 1 - - -.data -2048: .word 10 -2049: .word 10 -2050: .word 20 -2051: .word 30 -2052: .word 40 -2053: .word 50 -2054: .word 60 -2055: .word 70 -2056: .word 80 -2057: .word 90 -2058: .word 100 -2059: .word 3 -2060: .word 3 -2061: .word 3 -2062: .word 3 -2063: .word -2064: .word 11 -2065: .word 10 -2066: .word 20 -2067: .word 30 -2068: .word 40 -2069: .word 50 -2070: .word 60 -2071: .word 70 -2072: .word 80 -2073: .word 90 -2074: .word 100 -2075: .word 3 -2076: .word 3 -2077: .word 3 -2078: .word 3 -2079: .word 3 -2080: .word 5 - - diff --git a/pa3/unittests/beq_no_dep.asm b/pa3/unittests/beq_no_dep.asm deleted file mode 100644 index 894c249..0000000 --- a/pa3/unittests/beq_no_dep.asm +++ /dev/null @@ -1,22 +0,0 @@ -.text -addi $t0, $zero, 10 -addi $t1, $zero, 10 -addi $t2, $zero, 20 -addi $t3, $zero, 21 -addi $t4, $zero, 22 -addi $t5, $zero, 23 -beq $t0, $t1, loop -sw $t0, 2048($zero) -sw $t1, 2049($zero) -sw $t2, 2050($zero) -addi $t0, $zero, 30 - -loop: -lw $t0, 2048($zero) -addi, $zero, $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 5119 -2049: .word 32 - - diff --git a/pa3/unittests/fibonacci.asm b/pa3/unittests/fibonacci.asm deleted file mode 100644 index f086574..0000000 --- a/pa3/unittests/fibonacci.asm +++ /dev/null @@ -1,50 +0,0 @@ -.text -addi $t9, $zero, 10 -addi $t1, $zero, 0 -addi $t2, $zero, 1 -j fibonacci - -fibonacci: -add $t3, $t2, $t1 -add $t1, $zero, $t2 -add $t2, $zero, $t3 -addi $t5, $t5, 1 -bne $t5, $t9, fibonacci -addi $zero $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 10 -2049: .word 10 -2050: .word 20 -2051: .word 30 -2052: .word 40 -2053: .word 50 -2054: .word 60 -2055: .word 70 -2056: .word 80 -2057: .word 90 -2058: .word 100 -2059: .word 3 -2060: .word 3 -2061: .word 3 -2062: .word 3 -2063: .word -2064: .word 11 -2065: .word 10 -2066: .word 20 -2067: .word 30 -2068: .word 40 -2069: .word 50 -2070: .word 60 -2071: .word 70 -2072: .word 80 -2073: .word 90 -2074: .word 100 -2075: .word 3 -2076: .word 3 -2077: .word 3 -2078: .word 3 -2079: .word 3 -2080: .word 5 - - diff --git a/pa3/unittests/j_no_dep_test1.asm b/pa3/unittests/j_no_dep_test1.asm deleted file mode 100644 index 16aaf13..0000000 --- a/pa3/unittests/j_no_dep_test1.asm +++ /dev/null @@ -1,24 +0,0 @@ -.text -add $t0, $zero, $zero # iterator i = 0 -addi $t2, $zero, 1 # init t2 = 1 -add $t3, $zero, $zero # initialize temporary register to zero -add $t4, $zero, $zero # initialize temporary register to zero -j jump_test1 # Jump to procedure "jump_test1" - -jump_test2: -lw $a1, 2048($t0) # Load a1 = 2, Mem[2048] = 2, 2 in simulator -lw $a2, 2048($t2) # Load a2 = 10, Mem[2049] = 10, 10 in simulator -j end # Jump to procedure "end" - -jump_test1: -add $t5, $zero, $zero # initialize temporary register to zero -add $t6, $zero, $zero # initialize temporary register to zero -j jump_test2 # Jump to procedure "jump_test2" - -end: -addi, $zero, $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 2 -2049: .word 10 - diff --git a/pa3/unittests/jal_test1.asm b/pa3/unittests/jal_test1.asm deleted file mode 100644 index 6e7131d..0000000 --- a/pa3/unittests/jal_test1.asm +++ /dev/null @@ -1,23 +0,0 @@ -.text -addi $a0, $zero, 2 # argument 0 = 2 -addi $a1, $zero, 3 # argument 1 = 3 -addi $a2, $zero, 4 # argument 2 = 4 -addi $a3, $zero, 5 # argument 3 = 5 -add $t4, $zero, $zero -jal diffofsums # call procedure -addi, $zero, $zero, 1 # $zero register should never be updated, so detect this change and quit simulator -sll $zero, $zero, 1 # -sll $zero, $zero, 1 # - - - -diffofsums: -add $t0, $a0, $a1 # $t0 = f + g -add $t1, $a2, $a3 # $t1 = h + i -sub $s0, $t0, $t1 # result = (f+g)-(h+i) -add $v0, $s0, $zero # put return value in $v0 -jr $ra # return to caller - -.data -2048: .word 10 -2049: .word 10 diff --git a/pa3/unittests/lw_sw_test1.asm b/pa3/unittests/lw_sw_test1.asm deleted file mode 100644 index 2811d0c..0000000 --- a/pa3/unittests/lw_sw_test1.asm +++ /dev/null @@ -1,59 +0,0 @@ -.text -add $t0, $zero, $zero # i = 0 -add $t1, $zero, $zero # initialize the sum to zero -add $t2, $zero, $zero # for second loop compare 2 -add $t3, $zero, $zero -add $t5, $zero, $zero # initialize temporary register to zero -add $t6, $zero, $zero # for sw later -add $t7, $zero, $zero - -lw $t1, 2048($t0) # $t1=20 -lw $t2, 2048($t1) # $t2=4 -add $t4, $t1, $t2 # $t4=24 -lw $t3, 2048($t4) # $t3=8 -add $t4, $t4, $t3 # $t4=32 -sw $t4, 2048($t0) # mem[2048]=32 -lw $t1, 2048($t0) # $t1=32 <-- observation of stored value 32 as $t1=0x00000020 -lw $t2, 2048($t1) # $t2=5 -add $t4, $t1, $t2 # $t4=37 -sw $t4, 2048($t1) # mem[2080]=37 -lw $t5, 2048($t1) # $t5=37 <--- observation of stored value 37 as $t5=0x00000025 -addi, $zero, $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - - -.data -2048: .word 20 -2049: .word 32 -2050: .word 2 -2051: .word 2 -2052: .word 3 -2053: .word 3 -2054: .word 3 -2055: .word 3 -2056: .word 3 -2057: .word 3 -2058: .word 3 -2059: .word 3 -2060: .word 3 -2061: .word 3 -2062: .word 3 -2063: .word 3 -2064: .word 3 -2065: .word 3 -2066: .word 3 -2067: .word 3 -2068: .word 4 -2069: .word 3 -2070: .word 3 -2071: .word 3 -2072: .word 8 -2073: .word 3 -2074: .word 3 -2075: .word 3 -2076: .word 3 -2077: .word 3 -2078: .word 3 -2079: .word 3 -2080: .word 5 - - diff --git a/pa3/unittests/lw_sw_test2.asm b/pa3/unittests/lw_sw_test2.asm deleted file mode 100644 index a266623..0000000 --- a/pa3/unittests/lw_sw_test2.asm +++ /dev/null @@ -1,60 +0,0 @@ -.text -add $t0, $zero, $zero # i = 0 -add $t1, $zero, $zero # initialize the sum to zero -add $t2, $zero, $zero # for second loop compare 2 -add $t3, $zero, $zero -add $t5, $zero, $zero # initialize temporary register to zero -add $t6, $zero, $zero # for sw later -add $t7, $zero, $zero - -lw $t1, 2048($t0) # $t1=20 -add $t4, $t1, $t1 # $t4=40 -lw $t3, 2048($t4) # $t3=57 -addi, $zero, $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - - -.data -2048: .word 20 -2049: .word 32 -2050: .word 2 -2051: .word 2 -2052: .word 3 -2053: .word 3 -2054: .word 3 -2055: .word 3 -2056: .word 3 -2057: .word 3 -2058: .word 3 -2059: .word 3 -2060: .word 3 -2061: .word 3 -2062: .word 3 -2063: .word 3 -2064: .word 3 -2065: .word 3 -2066: .word 3 -2067: .word 3 -2068: .word 4 -2069: .word 3 -2070: .word 3 -2071: .word 3 -2072: .word 8 -2073: .word 3 -2074: .word 3 -2075: .word 3 -2076: .word 3 -2077: .word 3 -2078: .word 3 -2079: .word 3 -2080: .word 5 -2081: .word 50 -2082: .word 51 -2083: .word 52 -2084: .word 53 -2085: .word 54 -2086: .word 55 -2087: .word 56 -2088: .word 57 - - - diff --git a/pa3/unittests/no_dep_test1.asm b/pa3/unittests/no_dep_test1.asm deleted file mode 100644 index 619e23a..0000000 --- a/pa3/unittests/no_dep_test1.asm +++ /dev/null @@ -1,14 +0,0 @@ -.text -addi $t0, $zero, 10 -addi $t1, $zero, 25 -addi $t2, $zero, 20 -addi $t3, $zero, 19 -addi $t4, $zero, 18 -sw $t0, 2048($zero) -addi, $zero, $zero, 1 # $zero register should never be updated, so detect this change and quit simulator - -.data -2048: .word 5119 -2049: .word 32 - - diff --git a/pa4/Makefile b/pa4/Makefile deleted file mode 100644 index b17f6b5..0000000 --- a/pa4/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -SRCS = $(wildcard src/*.c) -HEADERS = $(wildcard src/*.h) -CC = gcc -CFLAGS = -g -std=c99 -LDFLAGS = -lm - -default: simulator - -simulator: $(SRCS) $(HEADERS) - @echo "Building $@..." - @echo "Sources: $(SRCS)" - @echo "Headers: $(HEADERS)" - $(CC) $(CFLAGS) -o $@ $(SRCS) $(LDFLAGS) - -clean: - -rm -f simulator - -rm -f pipe_trace.txt *.out mdump.txt cdump.txt diff --git a/pa4/README.md b/pa4/README.md deleted file mode 100644 index e7fdfca..0000000 --- a/pa4/README.md +++ /dev/null @@ -1,24 +0,0 @@ -# Programming Assignment 4: Pipelined riscy-uconn Simulator With Scoreboard Algorithm -A pipelined CPU simulator for the MIPS-like riscy-uconn instruction set architecture implementing a -scoreboard algorithm. The simulator translates machine code created by the riscy-uconn assembler, and executes -instructions one at a time. - -## Build Instructions - $ make - -## Usage - $ ./simulator assembled_program_file.out - -where `assembled_program_file.out` may be any assembled program file generated by the riscy-uconn -assembler. - -## Unit Tests -Several unit tests are provided in the `unittests` directory. These unit tests must be assembled -before use with the simulator by executing the following command: - - $ ../assembler/assembler unittests/unit_test_file.asm unittests/unit_test_file.out - -where `unit_test_file` is any of the unit test files (written in riscy-uconn assembly) in the -`unittests` directory. - - diff --git a/pa4/src/instruction_map.c b/pa4/src/instruction_map.c deleted file mode 100644 index b2f97d7..0000000 --- a/pa4/src/instruction_map.c +++ /dev/null @@ -1,40 +0,0 @@ -/** - * University of Connecticut - * CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 4: Pipelined riscy-uconn Simulator With Scoreboard - * - * riscy-uconn: instruction_map.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include "instruction_map.h" - -char* opcode_map[] = { - [RTYPEOP] = "RTYPEOP", - [LW] = "lw", - [SW] = "sw", - [ANDI] = "andi", - [ADDI] = "addi", - [ORI] = "ori", - [SLTI] = "slti", - [LUI] = "lui", - [BEQ] = "beq", - [BNE] = "bne", - [J] = "j", - [JAL] = "jal" -}; - -char* func_map[] = { - [ADD] = "add", - [SUB] = "sub", - [AND] = "and", - [OR] = "or", - [SLL] = "sll", - [SRL] = "srl", - [SLT] = "slt", - [JR] = "jr" -}; \ No newline at end of file diff --git a/pa4/src/instruction_map.h b/pa4/src/instruction_map.h deleted file mode 100644 index ba0e6c7..0000000 --- a/pa4/src/instruction_map.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * University of Connecticut - * CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 4: Pipelined riscy-uconn Simulator With Scoreboard - * - * riscy-uconn: instruction_map.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -extern char* opcode_map[]; -extern char* func_map[]; - -/* R-Type Instructions */ -#define RTYPEOP 0x0 -#define ADD 0x20 -#define SUB 0x21 -#define AND 0x24 -#define OR 0x25 -#define SLL 0x0 -#define SLT 0x2A -#define SRL 0x2 -#define JR 0x8 - -/* I-Type Instructions */ -#define LW 0x23 -#define SW 0x2B -#define ANDI 0xC -#define ORI 0xD -#define LUI 0xF -#define BEQ 0x4 -#define BNE 0x5 -#define SLTI 0xA -#define ADDI 0x8 - -/* J-Type Instructions */ -#define J 0x2 -#define JAL 0x3 \ No newline at end of file diff --git a/pa4/src/register_map.c b/pa4/src/register_map.c deleted file mode 100644 index 75cca0b..0000000 --- a/pa4/src/register_map.c +++ /dev/null @@ -1,49 +0,0 @@ -/** - * University of Connecticut - * CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 4: Pipelined riscy-uconn Simulator With Scoreboard - * - * riscy-uconn: register_map.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include "register_map.h" - -const char* register_map[] = { - [0] = "zero", - [1] = "at", - [2] = "v0", - [3] = "v1", - [4] = "a0", - [5] = "a1", - [6] = "a2", - [7] = "a3", - [8] = "t0", - [9] = "t1", - [10] = "t2", - [11] = "t3", - [12] = "t4", - [13] = "t5", - [14] = "t6", - [15] = "t7", - [16] = "s0", - [17] = "s1", - [18] = "s2", - [19] = "s3", - [20] = "s4", - [21] = "s5", - [22] = "s6", - [23] = "s7", - [24] = "t8", - [25] = "t9", - [26] = "k0", - [27] = "k1", - [28] = "gp", - [29] = "sp", - [30] = "fp", - [31] = "ra", -}; \ No newline at end of file diff --git a/pa4/src/register_map.h b/pa4/src/register_map.h deleted file mode 100644 index 617fd52..0000000 --- a/pa4/src/register_map.h +++ /dev/null @@ -1,16 +0,0 @@ -/** - * University of Connecticut - * CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 4: Pipelined riscy-uconn Simulator With Scoreboard - * - * riscy-uconn: register_map.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -extern const char* register_map[]; \ No newline at end of file diff --git a/pa4/src/sim_core.c b/pa4/src/sim_core.c deleted file mode 100644 index f7dcc0a..0000000 --- a/pa4/src/sim_core.c +++ /dev/null @@ -1,257 +0,0 @@ -/** - * University of Connecticut - * CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 4: Pipelined riscy-uconn Simulator With Scoreboard - * - * riscy-uconn: sim_core.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include -#include -#include - -#include "instruction_map.h" -#include "register_map.h" -#include "sim_core.h" -#include "sim_stages.h" -#include "util.h" - -/** - * Initial CPU state - */ -int cycle = 0; // CPU cycle -int registers[MAX_LENGTH] = {0}; // Registers -unsigned int pc = 0; // Program Counter (PC) register -int committed_instructions = 0; // Committed instructions -int *memory = NULL; // Data & instruction memory - -/* Pipeline related initialization */ -int br_taken = 0; - -/* Scoreboard related initialization */ -int register_result[MAX_LENGTH] = { [0 ... (MAX_LENGTH - 1)] = -1 }; // Scoreboard register results -int br_taken_instruction_number = 0; - -/* Instruction latencies */ -const int LATENCY_MEMORY = 3; -const int LATENCY_BRANCH = 1; -const int LATENCY_OTHER = 5; - -/** - * Utility - */ -FILE *fptr_pt; - -/** - * Simulator entry point - */ -int main(int argc, char *argv[]) { - if (argc != 2) { - fprintf(stderr, "[ERROR] incorrect number of arguments.\n"); - printf("usage: simulator PROGRAM_FILE\n"); - exit(1); - } else { - /* Open input program file */ - FILE *fp; - fp = fopen(argv[1], "r"); - - /* Open pipe trace */ - if (pipe_trace) { - fptr_pt = fopen("pipe_trace.txt", "w"); - } - - /* Initialize registers and instruction/data memory */ - initialize(fp); - - puts("\n"); - printf("Simulating...\n"); - - /* Process instructions one at a time */ - process_instructions(); - - puts(""); - - /* Output state after termination */ - rdump(); // Register dump - mdump(); // Memory dump - - /* Cleanup */ - free(memory); - free(scoreboard); - fclose(fp); - if (pipe_trace) { - fclose(fptr_pt); - } - - return 0; - } -} - -void process_instructions() { - int terminate = 0; - int instruction_counter = 0; //committed instruction count - - while (terminate != 1) { - /* Print information at cycle start */ - if (pipe_trace == 1) { - fprintf(fptr_pt, "Cycle: %d (Start)\n", cycle); - fprintf(fptr_pt, "PC: %d\n", pc); - fprintf(fptr_pt, "Committed Instructions: %d\n", committed_instructions); - fprintf(fptr_pt, "\n"); - - print_scoreboard(); - - fprintf(fptr_pt, "\n"); - rdump_pt(); - fprintf(fptr_pt, "\n"); - fprintf(fptr_pt, "=================================================================================================================================\n"); - fprintf(fptr_pt, "\n"); - - fflush(fptr_pt); - } - - /* Update state */ - write_result(); - execute(); - read_operands(); - issue(); - - /* Print information at cycle end */ - if (pipe_trace == 1) { - fprintf(fptr_pt, "Cycle: %d (End)\n", cycle); - fprintf(fptr_pt, "PC: %d\n", pc); - fprintf(fptr_pt, "Committed Instructions: %d\n", committed_instructions); - fprintf(fptr_pt, "\n"); - - print_scoreboard(); - - fprintf(fptr_pt, "\n"); - rdump_pt(); - fprintf(fptr_pt, "\n"); - fprintf(fptr_pt, "=================================================================================================================================\n"); - fprintf(fptr_pt, "\n"); - - fflush(fptr_pt); - } - - if (registers[0] != 0) { - terminate = 1; // set terminate flag when $zero is updated - } - - cycle++; // Increment cycle count - - /* Potential infinite loop detected */ - if (cycle == 10000) { - fprintf(stderr, "\n[WARNING] Simulation has simulated 10,000 cycles without terminating. Something might be wrong. Press CTRL + C to force termination.\n"); - } - } - printf("\nFinished simulation!\n"); - printf("\nTOTAL INSTRUCTIONS COMMITTED: %d\n", committed_instructions); - printf("TOTAL CYCLES SIMULATED: %d\n", cycle); -} - -void initialize(FILE *fp) { - printf("======================================\n"); - printf("=== BEGIN SIMULATOR INITIALIZATION ===\n"); - printf("======================================\n"); - if (fp == NULL) { - fprintf(stderr, "[ERROR] opening input file. Aborting.\n"); - exit(1); - } - - /* Zero initialize registers */ - memset(registers, 0, sizeof(registers)); - printf("Initialized Registers\n"); - - /* Allocate and zero-initialize scoreboard */ - scoreboard = (struct ScoreboardEntry*) calloc(SCOREBOARD_ENTRIES, sizeof(struct ScoreboardEntry)); - if (scoreboard == NULL) { - fprintf(stderr, "[ERROR] not enough memory. Aborting.\n"); - exit(1); - } - printf("Initialized Scoreboard\n"); - - /* Allocate instruction and data memory */ - memory = (int*) malloc(16384 * sizeof(int)); - if (memory == NULL) { - fprintf(stderr, "[ERROR] not enough memory. Aborting.\n"); - exit(1); - } - - /* Initialize memory to -1 */ - for (int i = 0; i < 16384; i++) { - memory[i] = -1; - } - printf("Initialized Memory\n"); - puts(""); - - printf("----------------------\n"); - printf("--- Section: .text ---\n"); - printf("----------------------\n"); - - /* Initialize parsing variables */ - char line[MAX_LENGTH + 2]; - char *p; - int i = 0, line_num = 0; - - /* Copy .text section to memory, break at nop */ - while (fgets(line, MAX_LENGTH + 2, fp) != NULL) { - line_num++; - - /* Remove '\n' from 'line' */ - p = strchr(line, '\n'); - if (p != NULL) { - *p = '\0'; - } - - memory[i] = getDec(line); - - /* If 'nop' found, move to 0x800 / 2048 in memory and break */ - if (strcmp(line, "11111111111111111111111111111111") == 0) { - memory[i] = 0; - i = 0x800; - break; - } else { - printf("memory[%d] = 0x%08x\n", i, memory[i]); - i++; - } - } - - int j = 2048; //Data Memory Starts at 2048 - for (j = i; j < 16384; j++) { - memory[j] = 0; - } - - puts(""); - - printf("----------------------\n"); - printf("--- Section: .data ---\n"); - printf("----------------------\n"); - - /* Seek fp to first instruction in .data */ - char data[MAX_LENGTH + 2]; - int bytes = 33 * line_num; - fseek(fp, bytes, SEEK_SET); - - /* Copy .data section to memory */ - while (fgets(line, MAX_LENGTH + 2, fp) != NULL) { - /* Remove '\n' from 'line' */ - p = strchr(line, '\n'); - if (p != NULL) { - *p = '\0'; - } - - memory[i] = getDec(line); - printf("memory[%d] = 0x%08x\n", i, memory[i]); - i++; - } - - printf("====================================\n"); - printf("=== END SIMULATOR INITIALIZATION ===\n"); - printf("===================================="); -} diff --git a/pa4/src/sim_core.h b/pa4/src/sim_core.h deleted file mode 100644 index ab14923..0000000 --- a/pa4/src/sim_core.h +++ /dev/null @@ -1,136 +0,0 @@ -/** - * University of Connecticut - * CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 4: Pipelined riscy-uconn Simulator With Scoreboard - * - * riscy-uconn: sim_core.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -#include - -extern FILE *fptr_pt; - -/* Max number of registers, and instruction length in bits */ -#define MAX_LENGTH 32 - -/* Array of registers (register file) */ -extern int registers[MAX_LENGTH]; - -/* Clock cycle */ -extern int cycle; - -/* Program Counter (PC) register */ -extern unsigned int pc; // Current PC - -/* Instruction and data memory */ -extern int *memory; - -/* Committed instructions */ -extern int committed_instructions; - -/* CPU state */ -struct State { - /* Fetched instruction */ - unsigned int inst; - - /* Decoded instruction fields */ - unsigned int opcode; - unsigned int func; - unsigned int rs; - unsigned int rt; - unsigned int rd; - unsigned int sa; - unsigned short imm; - - /* Memoryrelated */ - unsigned int mem_flag; - unsigned int mem_addr; - unsigned int mem_out; - - /* JAL related */ - unsigned int jmp_out_31; - - /* ALU */ - unsigned int alu_in1; - unsigned int alu_in2; - unsigned int alu_out; - - /* Scoreboard related */ - unsigned int pc_updated; -}; - -/* Pipeline related */ -extern int br_taken; - -/* Scoreboard related */ -#define SCOREBOARD_ENTRIES 100 - -extern int register_result[MAX_LENGTH]; -extern int br_taken_instruction_number; - -enum Stage {STAGE_INVALID, STAGE_ISSUE, STAGE_READ_OPERANDS, STAGE_EXECUTE, STAGE_WRITE_RESULT}; -enum Hazard {HAZARD_NONE, HAZARD_RAW, HAZARD_WAW, HAZARD_WAR, HAZARD_STRUCTURAL}; - -struct ScoreboardEntry { - /* Flag indicating if entry is valid */ - int valid; - - /* Instruction number of instruction corresponding to entry */ - int instruction_number; - - /* Pipeline stage of entry */ - enum Stage stage; - - /* Operation and sub-operation (for R-Type) instructions of entry */ - int operation; - int sub_operation; - - /* Hazard of entry (if any) */ - enum Hazard hazard; - - /* Source and destination register indices */ - int src_reg_1; - int src_reg_2; - int dest_reg; - - /* Source operand data */ - int src_reg_1_data; - int src_reg_2_data; - - /* Scoreboard entry that produces source operand data */ - int scb_1; - int scb_2; - - /* Flags indicating if source operands are available */ - int scb_1_ready; - int scb_2_ready; - - /* Immediate and shift amount for relevant instructions */ - int imm; - int sa; - - /* Branch/jump destination address */ - int br_address; - - /* Number of cycles spent in operation and operation latency */ - int cycles; - int latency; - - /* Operation result */ - int result; -} *scoreboard; - -/* Instruction latencies */ -extern const int LATENCY_MEMORY; -extern const int LATENCY_BRANCH; -extern const int LATENCY_OTHER; - -void initialize(FILE *fp); -void process_instructions(); \ No newline at end of file diff --git a/pa4/src/sim_stages.c b/pa4/src/sim_stages.c deleted file mode 100644 index 4ff0e8b..0000000 --- a/pa4/src/sim_stages.c +++ /dev/null @@ -1,70 +0,0 @@ -/** - * University of Connecticut - * CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * YOUR NAME HERE - * - * Programming Assignment 4: Pipelined riscy-uconn Simulator With Scoreboard - * - * riscy-uconn: sim_stages.c - * - */ - -#include -#include -#include -#include - -#include "instruction_map.h" -#include "sim_core.h" -#include "sim_stages.h" - -/** - * Debug flags - */ -int debug = 0; // Set to 1 for additional debugging information. -int pipe_trace = 1; // Set to 1 for pipe trace. - -/** - * Issue stage implementation. - */ -void issue(void) { - - /* Your code for the issue stage goes here. */ - -} - -/** - * Read Operands stage implementation. - */ -void read_operands(void) { - - /* Your code for the read operands stage goes here. */ - -} - -/** - * Execute stage implementation - */ -void execute(void) { - - /* Your code for the execute stage goes here. */ - -} - -/** - * Write Result stage implementation - */ -void write_result(void) { - - /* Your code for the write result stage goes here. */ - -} - -/** - * Advance PC. - * DO NOT MODIFY. - */ -void advance_pc(int step) { - pc += step; -} \ No newline at end of file diff --git a/pa4/src/sim_stages.h b/pa4/src/sim_stages.h deleted file mode 100644 index ce1dbfb..0000000 --- a/pa4/src/sim_stages.h +++ /dev/null @@ -1,25 +0,0 @@ -/** - * University of Connecticut - * CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 4: Pipelined riscy-uconn Simulator With Scoreboard - * - * riscy-uconn: sim_stages.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -#include "sim_core.h" - -extern int debug; -extern int pipe_trace; - -void issue(void); -void read_operands(void); -void execute(void); -void write_result(void); -void advance_pc(int step); \ No newline at end of file diff --git a/pa4/src/util.c b/pa4/src/util.c deleted file mode 100644 index 88bd87b..0000000 --- a/pa4/src/util.c +++ /dev/null @@ -1,305 +0,0 @@ -/** - * University of Connecticut - * CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 4: Pipelined riscy-uconn Simulator With Scoreboard - * - * riscy-uconn: util.c - * - * DO NOT MODIFY THIS FILE - * - */ - -#include -#include -#include -#include -#include - -#include "instruction_map.h" -#include "register_map.h" -#include "sim_core.h" - -static const char* stage_map[] = { - [STAGE_INVALID] = "Invalid", - [STAGE_ISSUE] = "Issue", - [STAGE_READ_OPERANDS] = "Read Operands", - [STAGE_EXECUTE] = "Execute", - [STAGE_WRITE_RESULT] = "Write Result" -}; - -/** - * Dump register contents. - * Will format for desired number of columns and output in specified file. - */ -void rdump_file_columns(FILE* file, unsigned columns) { - static const unsigned int index_col_width = 4; - static const unsigned int name_col_width = 5; - static const unsigned int value_col_width = 8; - static const unsigned int tab_spaces = 4; - static const unsigned int col_sep = 2; - - assert(columns > 0); - - /* Calculate number of rows and total row length*/ - const unsigned int rows = (int)ceil((double) MAX_LENGTH / columns); - const unsigned int row_length = columns * (index_col_width + name_col_width + value_col_width + 2 + 2 * tab_spaces) + (columns - 1) * (col_sep * tab_spaces); - - /* Print header */ - fprintf(file, "---------------------\n"); - fprintf(file, "--- Register Dump ---\n"); - fprintf(file, "---------------------\n"); - for (int col = 0; col < columns; col++) { - fprintf(file, "%-*s%-*s%-*s", index_col_width + tab_spaces, "Index", name_col_width + tab_spaces, "Name", value_col_width + 2, "Value"); - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - for (int col = 0; col < columns; col++) { - fprintf(file, "%-*s%-*s%-*s", index_col_width + tab_spaces, "-----", name_col_width + tab_spaces, "----", value_col_width + 2, "-----"); - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - - /* Print rows */ - for (int row = 0; row < rows; row++) { - for (int col = 0; col < columns; col++) { - unsigned int i = row + col * rows; - - if (i < MAX_LENGTH) { - fprintf(file, "$%-*i%*s$%-*s%*s0x%0*x", index_col_width, i, tab_spaces - 1, "", name_col_width, register_map[i], tab_spaces - 1, "", value_col_width, registers[i]); - } else { - fprintf(file, "\n"); - break; - } - - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - } - fprintf(file, "%-*s%*s%-*s%*s0x%08x\n", index_col_width, "N/A", tab_spaces, "", name_col_width, "pc", tab_spaces, "", pc); -} - -void rdump_pt() { - rdump_file_columns(fptr_pt, 4); -} - -void rdump() { - rdump_file_columns(stdout, 4); -} - -/** - * Dump memory contents. - */ -void mdump() { - FILE* fptr; - fptr = fopen("mdump.txt", "w"); - int i = 0; - for (i = 0; i < 16384; i++) { - fprintf(fptr, "Memory[%d] = 0x%08x\n", i, memory[i]); - } - fclose(fptr); -} - -/** - * Print instruction information - */ -void inst_dump(const char stage[], const unsigned int inst) { - int opcode = inst >> 26; - - unsigned int func = inst << 26; - func = func >> 26; - - int rs = (inst >> 21) & 0x1F; - int rt = (inst >> 16) & 0x1F; - int rd = (inst >> 11) & 0x1F; - int sa = (inst >> 6) & 0x1F; - int imm = inst & 0xFFFF; - short shortImm = (short)imm; - int target = inst & 0x03ffffff; - - fprintf(fptr_pt, "%-12s ", stage); - - if (inst == 0xffffffff) { - fprintf(fptr_pt, "INVALID INSTRUCTION\n"); - return; - } - - switch (opcode) { - case RTYPEOP: - switch (func) { - case JR: - fprintf(fptr_pt, "%-4s $%d\n", func_map[func], rs); - break; - - case SLL: - case SRL: - fprintf(fptr_pt, "%-4s $%d, $%d, %d\n", func_map[func], rd, rt, sa); - break; - - case ADD: - case SUB: - case AND: - case OR: - case SLT: - fprintf(fptr_pt, "%-4s $%d, $%d, $%d\n", func_map[func], rd, rs, rt); - break; - - default: - fprintf(fptr_pt, "INVALID INSTRUCTION\n"); - return; - break; - } - break; - - case LW: - case SW: - fprintf(fptr_pt, "%-4s $%d %d($%d)\n", opcode_map[opcode], rt, imm, rs); - break; - - case ANDI: - case ADDI: - case ORI: - case SLTI: - fprintf(fptr_pt, "%-4s $%d, $%d, %d\n", opcode_map[opcode], rt, rs, imm); - break; - - case LUI: - fprintf(fptr_pt, "%-4s $%d, %d\n", opcode_map[opcode], rt, imm); - break; - - case BEQ: - case BNE: - fprintf(fptr_pt, "%-4s $%d, $%d, %d\n", opcode_map[opcode], rs, rt, shortImm); - break; - - case J: - case JAL: - fprintf(fptr_pt, "%-4s %d\n", opcode_map[opcode], target); - break; - - default: - fprintf(fptr_pt, "INVALID INSTRUCTION\n"); - return; - break; - } -} - -void rresult_file_columns(FILE* file, unsigned columns) { - static const unsigned int index_col_width = 4; - static const unsigned int name_col_width = 5; - static const unsigned int value_col_width = 8; - static const unsigned int tab_spaces = 4; - static const unsigned int col_sep = 2; - - assert(columns > 0); - - /* Calculate number of rows and total row length*/ - const unsigned int rows = (int)ceil((double) MAX_LENGTH / columns); - const unsigned int row_length = columns * (index_col_width + name_col_width + value_col_width + 2 + 2 * tab_spaces) + (columns - 1) * (col_sep * tab_spaces); - - /* Print header */ - fprintf(file, "------------------------\n"); - fprintf(file, "--- Register Results ---\n"); - fprintf(file, "------------------------\n"); - for (int col = 0; col < columns; col++) { - fprintf(file, "%-*s%-*s%-*s", index_col_width + tab_spaces, "Index", name_col_width + tab_spaces, "Name", value_col_width, "Entry"); - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - for (int col = 0; col < columns; col++) { - fprintf(file, "%-*s%-*s%-*s", index_col_width + tab_spaces, "-----", name_col_width + tab_spaces, "----", value_col_width, "-----"); - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - - /* Print rows */ - for (int row = 0; row < rows; row++) { - for (int col = 0; col < columns; col++) { - unsigned int i = row + col * rows; - - if (i < MAX_LENGTH) { - fprintf(file, "$%-*i%*s$%-*s%*s%-*i", index_col_width, i, tab_spaces - 1, "", name_col_width, register_map[i], tab_spaces - 1, "", value_col_width, register_result[i]); - } else { - fprintf(file, "\n"); - break; - } - - if (col == columns - 1) { - fprintf(file, "\n"); - } else { - fprintf(file, "%*s", col_sep * tab_spaces, ""); - } - } - } -} - -/** - * Print scoreboard - */ -void print_scoreboard() { - fprintf(fptr_pt, "--------------------------\n"); - fprintf(fptr_pt, "--- Instruction Status ---\n"); - fprintf(fptr_pt, "--------------------------\n"); - fprintf(fptr_pt, "Instruction Number Stage Operation Sub-operation dest_reg src_reg_1 src_reg_2 scb_1 scb_2 scb_1_ready scb_2_ready\n"); - fprintf(fptr_pt, "------------------ ----- --------- ------------- -------- --------- --------- ----- ----- ----------- -----------\n"); - for (int i = 0; i < SCOREBOARD_ENTRIES; i++) { - struct ScoreboardEntry *entry = &scoreboard[i]; - - if (!entry->valid) { - continue; - } - - char const *ins = (entry->operation == RTYPEOP) ? func_map[entry->sub_operation] : opcode_map[entry->operation]; - char const *op = opcode_map[entry->operation]; - char const *subop = (entry->operation == RTYPEOP) ? func_map[entry->sub_operation] : "N/A"; - - fprintf(fptr_pt, "%-18i %-13s %-9s %-13s %-8i %-9i %-9i %-5i %-5i %-11s %-11s\n", - entry->instruction_number, stage_map[entry->stage], op, subop, entry->dest_reg, entry->src_reg_1, entry->src_reg_2, entry->scb_1, entry->scb_2, (entry->scb_1_ready) ? "yes" : "no", (entry->scb_2_ready) ? "yes" : "no"); - } - fprintf(fptr_pt, "\n"); - rresult_file_columns(fptr_pt, 3); -} - -/** - * Convert a binary string to an integer - */ -int getDec(char *bin) { - int b, k, m, n; - int len, sum = 0; - - len = strlen(bin) - 1; - - /* Iterate over the string */ - for (k = 0; k <= len; k++) { - // Convert char to numeric value - n = (bin[k] - '0'); - - // Check the character is binary - if ((n > 1) || (n < 0)) { - return 0; - } - - for (b = 1, m = len; m > k; m--) - b *= 2; - - // sum it up - sum = sum + n * b; - } - return sum; -} \ No newline at end of file diff --git a/pa4/src/util.h b/pa4/src/util.h deleted file mode 100644 index 7788a9e..0000000 --- a/pa4/src/util.h +++ /dev/null @@ -1,24 +0,0 @@ -/** - * University of Connecticut - * CSE 5302 / ECE 5402: Computer Architecture - * Fall 2021 - * - * Programming Assignment 4: Pipelined riscy-uconn Simulator With Scoreboard - * - * riscy-uconn: util.h - * - * DO NOT MODIFY THIS FILE - * - */ - -#pragma once - -#include - -void rdump_file_columns(FILE* file, unsigned columns); -void rdump(); -void rdump_pt(); -void mdump(); -void inst_dump(const char stage[], const unsigned int inst); -void print_scoreboard(); -int getDec(char *bin); \ No newline at end of file