Update by Jan.28th

Implemented Debug-Mode: support for break instruction, disassembly engine, and break-on-start option.
Modified License Year notice.

LICENSE

@@ -1,6 +1,6 @@
 MIT License
 
-Copyright (c) 2019-2020 Zero Tang
+Copyright (c) 2018-2021 Zero Tang
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

README.md

@@ -94,7 +94,7 @@ If it is your first time to build mipsivm, you will have to execute `build_prep.
 Currently, mipsivm supports 64-bit Windows.
 
 ### Windows
-To build mipsivm for Windows, you will need to install [Enterprise Windows Driver Kit 10](https://docs.microsoft.com/en-us/legal/windows/hardware/enterprise-wdk-license-2019) and mount it to T disk. Make sure you downloaded EWDK 10 version 2004 with Visual Studio Tools 16.7. <br>
+To build mipsivm for Windows, you will need to install [Enterprise Windows Driver Kit 10](https://docs.microsoft.com/en-us/legal/windows/hardware/enterprise-wdk-license-2019) and mount it to T disk. I recommend using [WinCDEmu](https://wincdemu.sysprogs.org/download/) to mount ISO image. Make sure you downloaded EWDK 10 version 2004 with Visual Studio Tools 16.7. <br>
 Execute `compchk_win10x64.bat` to compile mipsivm with `Debug/Checked` (unoptimized) compilation preset. <br>
 Execute `compfre_win10x64.bat` to compile mipsivm with `Release/Free` (optimized) compilation preset.
 

compchk_win10x64.bat

@@ -27,6 +27,12 @@ cl .\src\sim-i.c /I".\src\include" /Zi /nologo /W3 /WX /Oi /Od /D"_msvc" /D"_amd
 
 cl .\src\sim-j.c /I".\src\include" /Zi /nologo /W3 /WX /Oi /Od /D"_msvc" /D"_amd64" /D"_mips_simj" /Zc:wchar_t /Zc:forScope /FAcs /Fa"%objpath%\sim-j.cod" /Fo"%objpath%\sim-j.obj" /Fd"%objpath%\vc140.pdb" /Qspectre /GS- /Gd /TC /c /errorReport:queue
 
+cl .\src\disasm-r.c /I".\src\include" /Zi /nologo /W3 /WX /Oi /Od /D"_msvc" /D"_amd64" /D"_mips_disasmr" /Zc:wchar_t /Zc:forScope /FAcs /Fa"%objpath%\disasm-r.cod" /Fo"%objpath%\disasm-r.obj" /Fd"%objpath%\vc140.pdb" /Qspectre /GS- /Gd /TC /c /errorReport:queue
+
+cl .\src\disasm-i.c /I".\src\include" /Zi /nologo /W3 /WX /Oi /Od /D"_msvc" /D"_amd64" /D"_mips_disasmi" /Zc:wchar_t /Zc:forScope /FAcs /Fa"%objpath%\disasm-i.cod" /Fo"%objpath%\disasm-i.obj" /Fd"%objpath%\vc140.pdb" /Qspectre /GS- /Gd /TC /c /errorReport:queue
+
+cl .\src\disasm.c /I".\src\include" /Zi /nologo /W3 /WX /Oi /Od /D"_msvc" /D"_amd64" /D"_mips_disasm" /Zc:wchar_t /Zc:forScope /FAcs /Fa"%objpath%\disasm.cod" /Fo"%objpath%\disasm.obj" /Fd"%objpath%\vc140.pdb" /Qspectre /GS- /Gd /TC /c /errorReport:queue
+
 echo ============Start Linking============
 link "%objpath%\*.obj" /LIBPATH:"%libpath%\um\x64" /LIBPATH:"%libpath%\ucrt\x64" /LIBPATH:"%ddkpath%\lib\x64" /NOLOGO /DEBUG /PDB:"%objpath%\mipsivm.pdb" /INCREMENTAL:NO /OUT:"%binpath%\mipsivm.exe" /SUBSYSTEM:CONSOLE /Machine:X64 /ERRORREPORT:QUEUE
 

src/disasm-i.c

@@ -0,0 +1,144 @@
+/*
+  mipsivm - MIPS Interpreting Virtual Machine
+
+  Copyright(c) 2018-2021, Yaotian "Zero" Tang. All rights reserved.
+
+  This file takes charge of Disassembly Engine (I-Format).
+
+  This program is distributed in the hope that it will be useful, but 
+  without any warranty (no matter implied warranty or merchantability
+  or fitness for a particular purpose, etc.).
+
+  File Location: /disasm-i.c
+*/
+
+#include <midef.h>
+#include <mipsdef.h>
+#include <vmcb.h>
+#include <devkit.h>
+
+// Normal I-Format Instructions...
+void mips_disasm_i_beq(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"beq %s,%s,0x%X",mips_gpr_string[instruction.i.rs],mips_gpr_string[instruction.i.rt],pc+(imm<<2));
+}
+
+void mips_disasm_i_bne(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"bne %s,%s,0x%X",mips_gpr_string[instruction.i.rs],mips_gpr_string[instruction.i.rt],pc+(imm<<2));
+}
+
+void mips_disasm_i_blez(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"blez %s,0x%X",mips_gpr_string[instruction.i.rs],pc+(imm<<2));
+}
+
+void mips_disasm_i_bgtz(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"bgtz %s,0x%X",mips_gpr_string[instruction.i.rs],pc+(imm<<2));
+}
+
+void mips_disasm_i_addi(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"addi %s,%s,%d",mips_gpr_string[instruction.i.rs],mips_gpr_string[instruction.i.rt],imm);
+}
+
+void mips_disasm_i_addiu(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"addiu %s,%s,0x%X",mips_gpr_string[instruction.i.rs],mips_gpr_string[instruction.i.rt],instruction.i.imm);
+}
+
+void mips_disasm_i_slti(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"slti %s,%s,%d",mips_gpr_string[instruction.i.rs],mips_gpr_string[instruction.i.rt],imm);
+}
+
+void mips_disasm_i_sltiu(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"sltiu %s,%s,0x%X",mips_gpr_string[instruction.i.rs],mips_gpr_string[instruction.i.rt],instruction.i.imm);
+}
+
+void mips_disasm_i_andi(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const u32 imm=(u32)instruction.i.imm;
+	sim_snprintf(mnemonic,length,"andi %s,%s,0x%X",mips_gpr_string[instruction.i.rs],mips_gpr_string[instruction.i.rt],imm);
+}
+
+void mips_disasm_i_ori(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const u32 imm=(u32)instruction.i.imm;
+	sim_snprintf(mnemonic,length,"ori %s,%s,0x%X",mips_gpr_string[instruction.i.rs],mips_gpr_string[instruction.i.rt],imm);
+}
+
+void mips_disasm_i_xori(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const u32 imm=(u32)instruction.i.imm;
+	sim_snprintf(mnemonic,length,"xori %s,%s,0x%X",mips_gpr_string[instruction.i.rs],mips_gpr_string[instruction.i.rt],imm);
+}
+
+void mips_disasm_i_lui(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const u16 imm=(u16)instruction.i.imm;
+	sim_snprintf(mnemonic,length,"lui %s,%s,0x%X",mips_gpr_string[instruction.i.rs],mips_gpr_string[instruction.i.rt],imm);
+}
+
+void mips_disasm_i_lb(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"lb %s,%d(%s)",mips_gpr_string[instruction.i.rt],imm,mips_gpr_string[instruction.i.rs]);
+}
+
+void mips_disasm_i_lh(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"lh %s,%d(%s)",mips_gpr_string[instruction.i.rt],imm,mips_gpr_string[instruction.i.rs]);
+}
+
+void mips_disasm_i_lw(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"lw %s,%d(%s)",mips_gpr_string[instruction.i.rt],imm,mips_gpr_string[instruction.i.rs]);
+}
+
+void mips_disasm_i_lbu(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"lbu %s,%d(%s)",mips_gpr_string[instruction.i.rt],imm,mips_gpr_string[instruction.i.rs]);
+}
+
+void mips_disasm_i_lhu(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"lhu %s,%d(%s)",mips_gpr_string[instruction.i.rt],imm,mips_gpr_string[instruction.i.rs]);
+}
+
+void mips_disasm_i_sb(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"sb %s,%d(%s)",mips_gpr_string[instruction.i.rt],imm,mips_gpr_string[instruction.i.rs]);
+}
+
+void mips_disasm_i_sh(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"sh %s,%d(%s)",mips_gpr_string[instruction.i.rt],imm,mips_gpr_string[instruction.i.rs]);
+}
+
+void mips_disasm_i_sw(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"sw %s,%d(%s)",mips_gpr_string[instruction.i.rt],imm,mips_gpr_string[instruction.i.rs]);
+}
+
+// RegImm I-Format Instructions...
+void mips_disasm_i_bgez(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	const i32 imm=(i32)((i16)instruction.i.imm);
+	sim_snprintf(mnemonic,length,"bgez %s,0x%X",mips_gpr_string[instruction.i.rs],pc+(imm<<2));
+}

src/disasm-r.c

@@ -0,0 +1,173 @@
+/*
+  mipsivm - MIPS Interpreting Virtual Machine
+
+  Copyright(c) 2018-2021, Yaotian "Zero" Tang. All rights reserved.
+
+  This file takes charge of Disassembly Engine (R-Format).
+
+  This program is distributed in the hope that it will be useful, but 
+  without any warranty (no matter implied warranty or merchantability
+  or fitness for a particular purpose, etc.).
+
+  File Location: /disasm-r.c
+*/
+
+#include <midef.h>
+#include <mipsdef.h>
+#include <vmcb.h>
+#include <devkit.h>
+
+void mips_disasm_r_sll(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"sll %s,%s,%u",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rt],instruction.r.shamt);
+}
+
+void mips_disasm_r_srl(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"srl %s,%s,%u",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rt],instruction.r.shamt);
+}
+
+void mips_disasm_r_sra(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"sra %s,%s,%u",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rt],instruction.r.shamt);
+}
+
+void mips_disasm_r_sllv(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"sllv %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rt],mips_gpr_string[instruction.r.rs]);
+}
+
+void mips_disasm_r_srlv(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"srlv %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rt],mips_gpr_string[instruction.r.rs]);
+}
+
+void mips_disasm_r_srav(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"srav %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rt],mips_gpr_string[instruction.r.rs]);
+}
+
+void mips_disasm_r_jr(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"jr %s",mips_gpr_string[instruction.r.rs]);
+}
+
+void mips_disasm_r_jalr(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"jalr %s",mips_gpr_string[instruction.r.rs]);
+}
+
+void mips_disasm_r_movz(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"movz %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_movn(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"movn %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_syscall(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"syscall");
+}
+
+void mips_disasm_r_break(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"break");
+}
+
+void mips_disasm_r_sync(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"sync %s",mips_sync_type_string[instruction.r.shamt]);
+}
+
+void mips_disasm_r_mfhi(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"mfhi %s",mips_gpr_string[instruction.r.rd]);
+}
+
+void mips_disasm_r_mthi(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"mthi %s",mips_gpr_string[instruction.r.rs]);
+}
+
+void mips_disasm_r_mflo(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"mflo %s",mips_gpr_string[instruction.r.rd]);
+}
+
+void mips_disasm_r_mtlo(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"mtlo %s",mips_gpr_string[instruction.r.rs]);
+}
+
+void mips_disasm_r_mult(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"mult %s,%s",mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_multu(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"multu %s,%s",mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_div(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"div %s,%s",mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_divu(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"divu %s,%s",mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_add(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"add %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_addu(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"addu %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_sub(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"sub %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_subu(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"subu %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_and(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"and %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_or(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"or %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_xor(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"xor %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_nor(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"nor %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_slt(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"slt %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}
+
+void mips_disasm_r_sltu(char* mnemonic,u32 length,u32 pc,mips_instruction instruction)
+{
+	sim_snprintf(mnemonic,length,"sltu %s,%s,%s",mips_gpr_string[instruction.r.rd],mips_gpr_string[instruction.r.rs],mips_gpr_string[instruction.r.rt]);
+}