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Implemented many essential instructions. Implemented Memory Virtualization.
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Zero Tang
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Sep 19, 2020
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,2 +1,5 @@ | ||
| # Auto detect text files and perform LF normalization | ||
| * text=auto | ||
| *.c linguist-language=C | ||
| *.h linguist-language=C | ||
| *.asm linguist-language=Assembly |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,22 +1,25 @@ | ||
| /* | ||
| mipsivm - MIPS Interpreting Virtual Machine | ||
| Copyright 2018-2019, Yaotian "Zero" Tang. All rights reserved. | ||
| Copyright 2018-2020, Yaotian "Zero" Tang. All rights reserved. | ||
| This file is the entry module of mipsivm program. | ||
| This program is distributed in the hope that it will be useful, but | ||
| without any warranty (no matter implied warranty or merchantability | ||
| or fitness for a particular purpose, etc.). | ||
| File Location: /include/entry.c | ||
| File Location: /entry.c | ||
| */ | ||
|
|
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| #include <stdio.h> | ||
| #include <stdlib.h> | ||
| #include <string.h> | ||
| #include <stdarg.h> | ||
|
|
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| void main() | ||
| { | ||
| printf("Welcome to mipsivm!\n"); | ||
| printf("Powered by Yaotian \"Zero\" Tang. All rights reserved.\n"); | ||
| system("pause"); | ||
| } |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,225 @@ | ||
| /* | ||
| mipsivm - MIPS Interpreting Virtual Machine | ||
| Copyright 2018-2020, Yaotian "Zero" Tang. All rights reserved. | ||
| This file declares all simulated procedures. | ||
| This program is distributed in the hope that it will be useful, but | ||
| without any warranty (no matter implied warranty or merchantability | ||
| or fitness for a particular purpose, etc.). | ||
| File Location: /include/simulation.h | ||
| */ | ||
|
|
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| #include "midef.h" | ||
|
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| typedef void (*mips_interpreter_procedure) | ||
| ( | ||
| vmcb_p vcpu, | ||
| mips_instruction instruction | ||
| ); | ||
|
|
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| // R-Format Instructions | ||
| void mips_interpreter_r_sll(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_srl(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_sra(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_sllv(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_srlv(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_srav(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_jr(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_jalr(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_movz(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_movn(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_syscall(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_break(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_sync(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_mfhi(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_mthi(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_mflo(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_mtlo(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_mult(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_multu(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_div(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_divu(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_add(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_addu(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_sub(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_subu(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_and(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_or(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_xor(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_nor(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_slt(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_sltu(vmcb_p vcpu,mips_instruction instruction); | ||
|
|
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| // I-Format Instructions | ||
| void mips_interpreter_i_beq(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_bne(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_blez(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_bgtz(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_addi(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_addiu(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_slti(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_sltiu(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_andi(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_ori(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_xori(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_lui(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_lb(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_lh(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_lw(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_lbu(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_lhu(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_sb(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_sh(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_i_sw(vmcb_p vcpu,mips_instruction instruction); | ||
|
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| // J-Format Instructions | ||
| void mips_interpreter_j_j(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_j_jal(vmcb_p vcpu,mips_instruction instruction); | ||
|
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| // Miscellaneous | ||
| void mips_interpreter_unhandled_instruction(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_r_format(vmcb_p vcpu,mips_instruction instruction); | ||
| void mips_interpreter_fpu(vmcb_p vcpu,mips_instruction instruction); | ||
|
|
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| #if defined(_mips_hvm) | ||
| mips_interpreter_procedure cpu_interpreter_by_opcode[64]= | ||
| { | ||
| mips_interpreter_r_format, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_j_j, | ||
| mips_interpreter_j_jal, | ||
| mips_interpreter_i_beq, | ||
| mips_interpreter_i_bne, | ||
| mips_interpreter_i_blez, | ||
| mips_interpreter_i_bgtz, | ||
| mips_interpreter_i_addi, | ||
| mips_interpreter_i_addiu, | ||
| mips_interpreter_i_slti, | ||
| mips_interpreter_i_sltiu, | ||
| mips_interpreter_i_andi, | ||
| mips_interpreter_i_ori, | ||
| mips_interpreter_i_xori, | ||
| mips_interpreter_i_lui, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_fpu, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_i_lb, | ||
| mips_interpreter_i_lh, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_i_lw, | ||
| mips_interpreter_i_lbu, | ||
| mips_interpreter_i_lhu, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_i_sb, | ||
| mips_interpreter_i_sh, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_i_sw, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction | ||
| }; | ||
|
|
||
| mips_interpreter_procedure cpu_interpreter_r_funct[64]= | ||
| { | ||
| mips_interpreter_r_sll, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_r_srl, | ||
| mips_interpreter_r_sra, | ||
| mips_interpreter_r_sllv, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_r_srlv, | ||
| mips_interpreter_r_srav, | ||
| mips_interpreter_r_jr, | ||
| mips_interpreter_r_jalr, | ||
| mips_interpreter_r_movz, | ||
| mips_interpreter_r_movn, | ||
| mips_interpreter_r_syscall, | ||
| mips_interpreter_r_break, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_r_sync, | ||
| mips_interpreter_r_mfhi, | ||
| mips_interpreter_r_mthi, | ||
| mips_interpreter_r_mflo, | ||
| mips_interpreter_r_mtlo, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_r_mult, | ||
| mips_interpreter_r_multu, | ||
| mips_interpreter_r_div, | ||
| mips_interpreter_r_divu, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_r_add, | ||
| mips_interpreter_r_addu, | ||
| mips_interpreter_r_sub, | ||
| mips_interpreter_r_subu, | ||
| mips_interpreter_r_and, | ||
| mips_interpreter_r_or, | ||
| mips_interpreter_r_xor, | ||
| mips_interpreter_r_nor, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_r_slt, | ||
| mips_interpreter_r_sltu, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction, | ||
| mips_interpreter_unhandled_instruction | ||
| }; | ||
|
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||
| mips_interpreter_procedure fpu_interpreter[64]; | ||
| #endif |
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