removed error exceptions to test if itll work

jad13041 · Jan 23, 2020 · 5872f8e · 5872f8e
1 parent bb9a496
commit 5872f8e
Showing 1 changed file with 15 additions and 15 deletions.
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
@@ -254,8 +254,8 @@ l2_disabled:
 
 	li	r4,CriticalInput@l
 	mtspr	IVOR0,r4	/* 0: Critical input */
-	li	r4,MachineCheck@l
-	mtspr	IVOR1,r4	/* 1: Machine check */
+	//li	r4,MachineCheck@l
+	//mtspr	IVOR1,r4	/* 1: Machine check */
 	li	r4,DataStorage@l
 	mtspr	IVOR2,r4	/* 2: Data storage */
 	li	r4,InstStorage@l
@@ -266,8 +266,8 @@ l2_disabled:
 	mtspr	IVOR5,r4	/* 5: Alignment */
 	li	r4,ProgramCheck@l
 	mtspr	IVOR6,r4	/* 6: Program check */
-	li	r4,FPUnavailable@l
-	mtspr	IVOR7,r4	/* 7: floating point unavailable */
+	//li	r4,FPUnavailable@l
+	//mtspr	IVOR7,r4	/* 7: floating point unavailable */
 	li	r4,SystemCall@l
 	mtspr	IVOR8,r4	/* 8: System call */
 	/* 9: Auxiliary processor unavailable(unsupported) */
@@ -277,8 +277,8 @@ l2_disabled:
 	mtspr	IVOR11,r4	/* 11: Interval timer */
 	li	r4,WatchdogTimer@l
 	mtspr	IVOR12,r4	/* 12: Watchdog timer */
-	li	r4,DataTLBError@l
-	mtspr	IVOR13,r4	/* 13: Data TLB error */
+	//li	r4,DataTLBError@l
+	//mtspr	IVOR13,r4	/* 13: Data TLB error */
 	li	r4,InstructionTLBError@l
 	mtspr	IVOR14,r4	/* 14: Instruction TLB error */
 	li	r4,DebugBreakpoint@l
@@ -1244,7 +1244,7 @@ _start_of_vectors:
 	CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
 
 /* Machine check */
-	MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+	//MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 
 /* Data Storage exception. */
 	STD_EXCEPTION(0x0300, DataStorage, UnknownException)
@@ -1275,13 +1275,13 @@ ProgramCheck:
 
 	/* No FPU on MPC85xx.  This exception is not supposed to happen.
 	*/
-	STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
+	//STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
 	STD_EXCEPTION(0x0900, SystemCall, UnknownException)
 	STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
 	STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
 	STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
 
-	STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
+	//STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
 	STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
 
 	CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
@@ -1748,8 +1748,8 @@ trap_init:
 
 	lwz	r4,CriticalInput@got(r12)
 	mtspr	IVOR0,r4	/* 0: Critical input */
-	lwz	r4,MachineCheck@got(r12)
-	mtspr	IVOR1,r4	/* 1: Machine check */
+	//lwz	r4,MachineCheck@got(r12)
+	//mtspr	IVOR1,r4	/* 1: Machine check */
 	lwz	r4,DataStorage@got(r12)
 	mtspr	IVOR2,r4	/* 2: Data storage */
 	lwz	r4,InstStorage@got(r12)
@@ -1760,8 +1760,8 @@ trap_init:
 	mtspr	IVOR5,r4	/* 5: Alignment */
 	lwz	r4,ProgramCheck@got(r12)
 	mtspr	IVOR6,r4	/* 6: Program check */
-	lwz	r4,FPUnavailable@got(r12)
-	mtspr	IVOR7,r4	/* 7: floating point unavailable */
+	//lwz	r4,FPUnavailable@got(r12)
+	//mtspr	IVOR7,r4	/* 7: floating point unavailable */
 	lwz	r4,SystemCall@got(r12)
 	mtspr	IVOR8,r4	/* 8: System call */
 	/* 9: Auxiliary processor unavailable(unsupported) */
@@ -1771,8 +1771,8 @@ trap_init:
 	mtspr	IVOR11,r4	/* 11: Interval timer */
 	lwz	r4,WatchdogTimer@got(r12)
 	mtspr	IVOR12,r4	/* 12: Watchdog timer */
-	lwz	r4,DataTLBError@got(r12)
-	mtspr	IVOR13,r4	/* 13: Data TLB error */
+	//lwz	r4,DataTLBError@got(r12)
+	//mtspr	IVOR13,r4	/* 13: Data TLB error */
 	lwz	r4,InstructionTLBError@got(r12)
 	mtspr	IVOR14,r4	/* 14: Instruction TLB error */
 	lwz	r4,DebugBreakpoint@got(r12)