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input result from function manually
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jad13041 committed Feb 6, 2020
1 parent 05d6b58 commit a9e05a8
Showing 1 changed file with 3 additions and 12 deletions.
15 changes: 3 additions & 12 deletions drivers/ddr/fsl/main.c
Expand Up @@ -619,8 +619,6 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,

phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
{
printf("debug point 1\n");
mdelay(2000);
unsigned int i, first_ctrl, last_ctrl;
#ifdef CONFIG_PPC
unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
Expand All @@ -630,8 +628,6 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)

first_ctrl = pinfo->first_ctrl;
last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
printf("debug point 2\n");
mdelay(2000);
/* Compute it once normally. */
#ifdef CONFIG_FSL_DDR_INTERACTIVE
if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */
Expand All @@ -654,8 +650,6 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
default:
break;
}
printf("debug point 3\n");
mdelay(2000);
/*
* Program configuration registers.
* JEDEC specs requires clocks to be stable before deasserting reset
Expand Down Expand Up @@ -686,8 +680,6 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
deassert_reset ? 1 : 0);
}
printf("debug point 4\n");
mdelay(2000);
if (deassert_reset) {
/* Use board FPGA or GPIO to deassert reset signal */
if (pinfo->board_mem_de_reset) {
Expand All @@ -702,8 +694,7 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
i, 2);
}
}
printf("debug point 5\n");
mdelay(2000);
//here still no change
#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
#endif
Expand Down Expand Up @@ -780,7 +771,7 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
}
}
#endif
printf("debug point 6\n");
printf("debug point, by now ram has changed\n");
mdelay(2000);

printf("total_memory by %s = %llu\n", __func__, total_memory);
Expand Down Expand Up @@ -847,7 +838,7 @@ phys_size_t fsl_other_ddr_sdram(unsigned long long base,
info.board_mem_reset = board_reset;
info.board_mem_de_reset = board_de_reset;

return __fsl_ddr_sdram(&info);
return 8589934592;//__fsl_ddr_sdram(&info);
}
#endif

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