Fix

core_sc.py

@@ -84,43 +84,52 @@ class Core_SC:
             # Preapre RF write
             # Compute PC_new
             self.RF.set_read_registers(self.signals.rs, self.signals.rt)
-            self.RF.set_write_register(self.signals.Write_register)
-            self.RF.set_regwrite(self.signals.RegWrite)
 
-            ##ALU
-            self.signals.ALU_input_2 = MUX_2_1(self.RF.get_read_data_2(),
+            self.signals.RF_read_data_1 = self.RF.get_read_data_1()
+            self.signals.RF_read_data_2 = self.RF.get_read_data_2()
+
+            self.signals.ALU_input_2 = MUX_2_1(self.signals.RF_read_data_2,
                                                self.signals.Sign_extended_immediate,
                                                self.signals.ALUSrc)
-            self.signals.ALU_returned_value = ALU_32(self.RF.get_read_data_1(),
+
+            self.signals.ALU_returned_value = ALU_32(self.signals.RF_read_data_1,
                                                      self.signals.ALU_input_2,
                                                      self.signals.ALU_operation
                                                      )
 
-            ##Data memory
-            self.D_Mem.set_address(self.signals.ALU_returned_value[0])
 
-            self.D_Mem.set_memwrite(self.RF.get_read_data_2())
+            self.signals.ALU_result = self.signals.ALU_returned_value[0]
+            self.signals.Zero = self.signals.ALU_returned_value[1]
 
+            self.RF.set_write_register(self.signals.Write_register)
+            self.RF.set_regwrite(self.signals.RegWrite)
+
+            ##Data memory
+            self.D_Mem.set_address(self.signals.ALU_result)
+            self.D_Mem.set_data(self.signals.RF_read_data_2)
             self.D_Mem.set_memread(self.signals.MemRead)
+            self.D_Mem.set_memwrite(self.signals.MemWrite)
 
+            self.D_Mem.run()
             ##Write data
+            self.signals.MEM_read_data = self.D_Mem.get_data()
 
-            self.signals.Write_data = MUX_2_1(self.D_Mem.get_data(),
-                                              self.signals.ALU_returned_value[0],
+            self.signals.Write_data = MUX_2_1(self.signals.ALU_result,
+                                              self.signals.MEM_read_data,
                                               self.signals.MemtoReg
                                               )
             self.RF.set_write_data(self.signals.Write_data)
 
             ##PC
             self.signals.PCSrc = AND_2(self.signals.Branch,
-                                       self.signals.ALU_returned_value[1]
+                                       self.signals.Zero
                                        )
             self.signals.PC_branch = MUX_2_1(self.signals.PC_4,
                                              self.signals.Branch_address,
                                              self.signals.PCSrc
                                              )
-            self.signals.PC_new = MUX_2_1(self.signals.Jump_address,
-                                          self.signals.PC_branch,
+            self.signals.PC_new = MUX_2_1(self.signals.PC_branch,
+                                          self.signals.Jump_address,
                                           self.signals.Jump
                                           )
 
@@ -130,6 +139,7 @@ class Core_SC:
 
             # Print out signals generated in Phase 2.
             if ((self.mode & 8) == 0): utilities.print_signals_2(self.signals)
+            ##break
         return i_cycles
 
     def signals_from_instruction (self, instruction, sig):

tv01.txt

@@ -0,0 +1,17 @@
+ Address    Code        Basic                     Source
+
+0x00400000  0x20010001  addi $1,$0,0x00000001 10   	addi	$1,  $0,  1
+0x00400004  0x0381e020  add $28,$28,$1        11   	add	$28, $28, $1
+0x00400008  0x2002fffe  addi $2,$0,0xfffffffe 13   	addi	$2,  $0,  -2
+0x0040000c  0x0381e020  add $28,$28,$1        14   	add	$28, $28, $1
+0x00400010  0x00221825  or $3,$1,$2           16   	or	$3,  $1,  $2
+0x00400014  0x00232024  and $4,$1,$3          17   	and	$4,  $1,  $3
+0x00400018  0x2005000a  addi $5,$0,0x0000000a 19   	addi	$5,  $0,  10
+0x0040001c  0x10a0fff8  beq $5,$0,0xfffffff8  21   	beq	$5,  $0,  main
+0x00400020  0x10a50005  beq $5,$5,0x00000005  22   	beq	$5,  $5,  end
+0x00400024  0x00852822  sub $5,$4,$5          24   	sub	$5,  $4,  $5
+0x00400028  0x20c603e8  addi $6,$6,0x000003e8 25   	addi	$6,  $6, 1000
+0x0040002c  0x8cc7fffc  lw $7,0xfffffffc($6)  26   	lw	$7, -4($6)
+0x00400030  0xacc80064  sw $8,0x00000064($6)  27   	sw	$8, 100($6)
+0x00400034  0x0810000f  j 0x0040003c          28   	j	exit
+0x00400038  0x08100009  j 0x00400024          30   	j	back