Programming Assignment 3: Pipelined riscy-uconn Simulator with Multi-cycle Operations and Data Cache
A 5-stage pipelined CPU simulator with multi-cycle operations and data cache for the MIPS-like riscy-uconn instruction set architecture. The simulator translates machine code created by the riscy-uconn assembler, and executes instructions one at a time. Each instruction goes through a Fetch, Decode, Execute, Memory and Writeback stage of processing.
Build Instructions
$ make
Usage
$ ./simulator assembled_program_file.out FORWARDING_ENABLED DATA_CACHE_ENABLED
where assembled_program_file.out may be any assembled program file generated by the riscy-uconn
assembler, FORWARDING_ENABLED may be 0 (disabled) or 1 (enabled), and DATA_CACHE_ENABLED may be
0 (disabled) or 1 (enabled).
Unit Tests
Several unit tests are provided in the unittests directory. These unit tests must be assembled
before use with the simulator by executing the following command:
$ ../assembler/assembler unittests/unit_test_file.asm unittests/unit_test_file.out
where unit_test_file is any of the unit test files (written in riscy-uconn assembly) in the
unittests directory.