sim_stages.c

/**
 * University of Connecticut
 * CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture
 * Fall 2023
 * TODO: YOUR NAME HERE
 * 
 * Programming Assignment 3: Dynamic Branch Prediction & Set Associative Cache
 * 
 * riscy-uconn: sim_stages.c
 * 
 */
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "instruction_map.h"
#include "sim_core.h"
#include "sim_stages.h"

/**
 * Debug flags
 */
int debug = 0;           /* Set to 1 for additional debugging information. */
int pipe_trace = 1;      /* Set to 1 for pipe trace. */
int pipe_trace_mode = 3; /* See PA1 handout, section 5 for usage */

/**
 * Fetch stage implementation.
 */
struct State fetch(void) {
    /* Use the current PC to store i) The instruction ii) The instruction address */
    struct State fetch_out = {0};
    fetch_out.inst = memory[pc / 4];
    fetch_out.inst_addr = pc;
    
    /* Pipeline must be flushed */
    if (/** TODO: Your logic for pipe flush here **/) {
        return nop;
    }

    /* Pipeline is stalled  */
    else if (/**TODO: Your logic for pipe stall here **/){
        return fetch_out;
    }

    /** TODO: Your branch prediction implementation here  **/
    
    /* Return the instruction */
    return fetch_out;
}

/**
 * Decode stage implementation
 */
struct State decode(struct State fetch_out) {
    
    /** TODO: Insert your logic for the decode stage **/

    return fetch_out; 
}

/**
 * Execute stage implementation
 */
struct State execute(struct State decode_out) {
    
    /** TODO: Insert your logic for the execute stage **/
    
    return decode_out;
}

/**
 * Memory stage implementation
 */
struct State memory_stage(struct State ex_out) {
    
    /** TODO: Insert your logic for the memory stage **/
    
    return ex_out;
}

/**
 * Writeback stage implementation
 */
unsigned int writeback(struct State mem_out) {

    /** TODO: Insert your logic for the writeback stage **/

    return mem_out.inst;
}

/*******************************/
/* BRANCH PREDICTION FUNCTIONS */
/*******************************/

/**
 * Branch target buffer hit lookup:
*/
unsigned int BTB_lookup(unsigned int inst_addr){
    
    /** TODO: Your implementation for the BTB_lookup() function here **/

}

/**
 * Branch target buffer target address lookup
*/
unsigned int BTB_target(unsigned int inst_addr){
    
    /** TODO: Your implementation of the BTB_target() function here **/

}

/**
 * Branch target buffer entry update 
 */
void BTB_update(unsigned int inst_addr, unsigned int branch_target){
    
    /** TODO: Your implementation of the BTB_update() function here **/

}

/** 
 * BHT predictor lookup
*/
unsigned int predict_direction(void){
    
    /** TODO: Your implementation of the predict_direction() function here **/

}

/**
 * BHT and BHSR update 
*/
void direction_update(unsigned int direction){
    
    /** TODO: Your implementation of the direction_update() function here **/

}

/************************/
/* DATA CACHE FUNCTIONS */
/************************/

/**
 * Data cache lookup
 */
unsigned int dcache_lookup(unsigned int addr_mem) {

    /** TODO: Your implementation of dcache_lookup() here **/

}

/**
 * Data cache update
 */
void dcache_update(unsigned int addr_mem) {
    
    /** TODO: Your implementation of the dcache_update() function here **/

}

/**
 * Advance PC.
 * DO NOT MODIFY.
 */
void advance_pc(int step) {
    pc_n = pc + step;
}

/**
 * Update the states of the simulator.
 * DO NOT MODIFY.
 */
void update_simulator_state() {
    
    /* Stall every stage and overwrite memory for correct pipe trace */
    if (dmem_busy) {
        mem_out = nop;
    
    /* Hold the old values of pc and fetch_out. */
    /* Inject NOP into decode_out, allow following stages to proceed. */
    }else if (pipe_stall) {    
        decode_out = nop; 
        ex_out     = ex_out_n;
        mem_out    = mem_out_n;

    /* No stalls, so advance every stage down the pipeline */
    }else {
        pc          = pc_n;
        fetch_out   = fetch_out_n;
        decode_out  = decode_out_n;
        ex_out      = ex_out_n;
        mem_out     = mem_out_n;
    }
}