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/**
* University of Connecticut
* CSE 4302 / ECE 5402: Computer Architecture
* Fall 2023
*
* Programming Assignment 1: Non-pipelined Simulator
*
* riscy-uconn: instruction_map.h
*
* DO NOT MODIFY THIS FILE
*
*/
#pragma once
/* Opcode Bits */
#define RTYPE 0x33
#define ITYPE_ARITH 0x13
#define ITYPE_LOAD 0x3
#define STYPE 0x23
#define BTYPE 0x63
#define LUI 0x37
#define JAL 0x6F
#define JALR 0x67
/* Funct3 Bits */
/* R and I-Type Arithmetic */
#define ADD_SUB 0b000
#define SUB 0b000
#define SLT 0b010
#define SLL 0b001
#define SRL 0b101
#define AND 0b111
#define OR 0b110
#define XOR 0b100
/* I-type JALR and Load, S-type, and B-type */
#define LW_SW 0b010
#define BEQ 0b000
#define BNE 0b001
#define BLT 0b100
#define BGE 0b101
/* R-type Funct7s */
#define ADD_F7 0x0
#define SUB_F7 0x20