.

assembler/README.md

@@ -1,52 +1,41 @@
-RISC-V Assembler
+Mips Assembler
 ==============
 
-An assembler for a subset of the RISC-V instruction set architecture
+An assembler for a subset of the MIPS like instruction set architecture
 
 # How to use
-The assembler will take a file written in assembly language as an input on the command line, and will produce an output file containing the RISC-V machine code. The input file should be in ASCII text. Each line in the input assembly file contains either a mnemonic, a section header (such as .data) or a label (jump or branch target). The maximum length of a line is 4 bytes. Section headers such as .data and .text should be in a line by themselves with no other assembly mnemonic. Similarly, branch targets such as loop: will be on a line by themselves with no other assembly mnemonic. The input assembly file should only contain one data section and one text section. The first section in the file will be the .text section, followed by the .data section.
+The assembler will take a file written in assembly language as input on the command line and will produce an output file containing the MIPS machine code. The input file should be in ASCII text. Each line in the input assembly file contains either a mnemonic, a section header (such as .data) or a label (jump or branch target. The maximum length of a line is 4 bytes. Section headers such as .data and .text should be in a line by themselves with no other assembly mnemonic. Similarly, branch targets such as loop: will be on a line by themselves with no other assembly mnemonic. The input assembly file should only contain one data section and one text section. The first section in the file will be the .text section, followed by the .data section.
 
 The assembler supports the following instruction set:
 
 R-Type
 - add
 - sub
-- slt
-- sll
-- srl
 - and
 - or
-- xor
+- sll
+- slt
+- srl
+- jr
 
 I-Type
-- jalr
+- lw
+- sw
+- andi
 - addi
 - slti
-- andi
 - ori
-- xori
-- slli
-- srli
-- lw
-
-S-Type
-- sw
-
-B-Type
+- lui
 - beq
 - bne
-- blt
-- bge
 
 J-Type
+- j
 - jal
 
-U-Type
-- lui
-
 # Run
     to compile the assembler
-    $ make
+    $ ./make
 
     to run the assembler on a nop.asm assembly file to write machine code in nop.out
     $ ./assembler nop.asm nop.out

assembler/file_parser.c

@@ -26,13 +26,13 @@ struct {
 	{ "x0", "zero", "00000" },
 	{ "x1", "ra",   "00001" },
 	{ "x2", "sp",   "00010" },
-	{ "x3",  "gp",  "00011" }, 
-	{ "x4",  "tp",  "00100" }, 
-	{ "x5",  "t0",  "00101" },
-	{ "x6",  "t1",  "00110" },
-	{ "x7",  "t2",  "00111" },
-	{ "x8",  "s0",  "01000" },
-	{ "x9",  "s1",  "01001" },
+	{ "x3", "gp",   "00011" }, 
+	{ "x4", "tp",   "00100" }, 
+	{ "x5", "t0",   "00101" },
+	{ "x6", "t1",   "00110" },
+	{ "x7", "t2",   "00111" },
+	{ "x8", "s0",   "01000" },
+	{ "x9", "s1",   "01001" },
 	{ "x10", "a0",  "01010" },
 	{ "x11", "a1",  "01011" },
 	{ "x12", "a2",  "01100" },
@@ -55,7 +55,7 @@ struct {
 	{ "x29", "t4",  "11101" },
 	{ "x30", "t5",  "11110" },
 	{ "x31", "t6",  "11111" },
-	{ NULL,  NULL,  0       } 
+	{ NULL,  NULL,  0 } 
 };
 
 // Struct for R-Type instructions mapping for the 'function' field in the instruction
@@ -73,7 +73,7 @@ struct {
 	{ "and", "0000000", "111", "0110011" },
 	{ "or",  "0000000", "110", "0110011" },
 	{ "xor", "0000000", "100", "0110011" },
-	{ NULL,  0 } 
+	{ NULL,  NULL,      NULL,  NULL      } 
 };
 
 // Struct for I-Type instructions
@@ -503,7 +503,7 @@ void parse_file(FILE *fptr, int pass, char *instructions[], size_t inst_len, has
 
 							// rs1 in position 0, rs2 in position 1
 							int immediate = (*address - instruction_count + 4) >> 1; //What in tarnation?
-							btype_instruction(token, reg_store[1], reg_store[0], immediate, Out);
+							btype_instruction(token, reg_store[0], reg_store[1], immediate, Out);
 
 							// Dealloc reg_store
 							for (int i = 0; i < 2; i++) {

pa1/Makefile

@@ -0,0 +1,19 @@
+SRCS = $(wildcard src/*.c)
+HEADERS = $(wildcard src/*.h)
+CC = gcc
+CFLAGS = -g -std=c99
+LDFLAGS = -lm
+
+default: simulator
+
+simulator: $(SRCS) $(HEADERS)
+	@echo "Building $@..."
+	@#gcc simulator.o -o simulator -ggdb -std=c99
+	@echo "Sources: $(SRCS)"
+	@echo "Headers: $(HEADERS)"
+	$(CC) $(CFLAGS) -o $@ $(SRCS) $(LDFLAGS)
+
+clean:
+	-rm -r assembled_tests
+	-rm -f simulator
+	-rm -f pipe_trace.txt *.out mdump.txt

pa1/README.md

@@ -0,0 +1,27 @@
+# Programming Assignment 1: Non-pipelined riscy-uconn Simulator
+
+A non-pipelined CPU simulator for the RISC-V riscv-uconn instruction set architecture. The
+simulator translates machine code created by the riscv-uconn assembler, and executes instructions
+one at a time. Each instruction goes through a Fetch, Decode, Execute, Memory, and Writeback stage of
+processing.
+
+## Build Instructions
+    $ make
+
+## Unit Tests
+Several unit tests are provided in the `unittests` directory. These unit tests must be assembled
+before use with the simulator. Ensure that the assembler is compiled (this should be done after completing PA0). 
+The unit tests can all be assembled by executing the following command:
+
+    $ ../assembler/assembler unittests/unit_test_file.asm unittests/unit_test_file.out
+
+where `unit_test_file` is any of the unit test files (written in riscy-uconn assembly) in the
+`unittests` directory. Note that you do not need to store the output files in the `unittests` directory. You may also use the provided `assemble_all.sh' script:
+
+    $ bash assemble_all.sh
+
+## Usage
+    $ ./simulator unittests/unit_test_file.out
+
+where `unit_test_file.out` may be any assembled program file generated by the riscy-uconn
+assembler.

pa1/assemble_all.sh

@@ -0,0 +1,19 @@
+#!/bin/bash
+
+# This script is privided to you to assemble all unit tests for you.
+# 1) First ensure that that your assembler is compiled
+# 2) Then, run "$ bash assemble_all.sh". 
+# A new directory "assembled tests will be generated, populated with all the binary tests.
+# Note: "$ make clean" will remove these tests
+
+if [ ! -d assembled_tests ]; then
+	echo "Creating \"assembled_tests\" directory..."
+	mkdir assembled_tests
+fi
+
+for test in unittests/*.asm; do
+	echo "Assembling test \"$test\"..."
+	testname=$(basename $test .asm)
+	../assembler/assembler $test assembled_tests/$testname.out > /dev/null 2>&1
+done
+echo "Done!"

pa1/src/instruction_map.h

@@ -0,0 +1,62 @@
+/**
+ * University of Connecticut
+ * CSE 4302/ CSE 5302 / ECE 5402: Computer Architecture
+ * Fall 2023
+ * 
+ * Programming Assignment 1: Non-pipelined Simulator
+ * 
+ * riscy-uconn: sim_stages.c
+ * 
+ * DO NOT MODIFY THIS FILE
+ * 
+ */
+
+
+#pragma once
+
+/* Some helpful defines for decoding instructions */
+#define bit_7            0x00000080
+#define bit_31           0x80000000
+#define bit_20           0x00100000
+#define bit_2_downto_0   0x00000007
+#define bit_4_downto_0   0x0000001F
+#define bit_6_downto_0   0x0000007F
+#define bit_10_downto_7  0x00000780
+#define bit_11_downto_8  0x00000F00
+#define bit_19_downto_12 0x000FF000
+#define bit_30_downto_21 0x7FE00000
+#define bit_30_downto_25 0x7E000000
+#define bit_31_downto_12 0xFFFFF000
+#define bit_31_downto_20 0xFFF00000
+#define bit_31_downto_25 0xFE000000
+
+/* Opcode Bits */
+#define RTYPE        0x33
+#define ITYPE_ARITH  0x13
+#define ITYPE_LOAD   0x3
+#define STYPE        0x23
+#define BTYPE        0x63
+#define LUI          0x37
+#define JAL          0x6F
+#define JALR         0x67
+
+/* Funct3 Bits */
+/* R and I-Type Arithmetic */
+#define ADD_SUB      0b000
+#define SUB          0b000
+#define SLT          0b010
+#define SLL          0b001
+#define SRL          0b101
+#define AND          0b111
+#define OR           0b110
+#define XOR          0b100
+/* I-type JALR and Load, S-type, and B-type */
+#define LW_SW        0b010
+#define BEQ          0b000
+#define BNE          0b001
+#define BLT          0b100
+#define BGE          0b101
+
+/* R-type Funct7s */
+#define ADD_F7       0x0
+#define SUB_F7       0x20

pa1/src/register_map.c

@@ -0,0 +1,50 @@
+/**
+ * University of Connecticut
+ * CSE 4302/ CSE 5302 / ECE 5402: Computer Architecture
+ * Fall 2023
+ * 
+ * Programming Assignment 1: Non-pipelined Simulator
+ * 
+ * riscy-uconn: sim_stages.c
+ * 
+ * DO NOT MODIFY THIS FILE
+ * 
+ */
+
+
+#include "register_map.h"
+
+const char* register_map[] = {
+     [0]  = "zero",
+     [1]  = "ra",
+     [2]  = "sp",
+     [3]  = "gp",
+     [4]  = "tp",
+     [5]  = "t0",
+     [6]  = "t1",
+     [7]  = "t2",
+     [8]  = "s0",
+     [9]  = "s1",
+     [10] = "a0",
+     [11] = "a1",
+     [12] = "a2",
+     [13] = "a3",
+     [14] = "a4",
+     [15] = "a5",
+     [16] = "a6",
+     [17] = "a7",
+     [18] = "s2",
+     [19] = "s3",
+     [20] = "s4",
+     [21] = "s5",
+     [22] = "s6",
+     [23] = "s7",
+     [24] = "s8",
+     [25] = "s9",
+     [26] = "s10",
+     [27] = "s11",
+     [28] = "t3",
+     [29] = "t4",
+     [30] = "t5",
+     [31] = "t6",
+};

pa1/src/register_map.h

@@ -0,0 +1,16 @@
+/**
+ * University of Connecticut
+ * CSE 4302/ CSE 5302 / ECE 5402: Computer Architecture
+ * Fall 2023
+ * 
+ * Programming Assignment 1: Non-pipelined Simulator
+ * 
+ * riscy-uconn: sim_stages.c
+ * 
+ * DO NOT MODIFY THIS FILE
+ * 
+ */
+
+#pragma once
+
+extern const char* register_map[];