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cag-uconn committed Sep 12, 2022
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19 changes: 19 additions & 0 deletions pa1/Makefile
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SRCS = $(wildcard src/*.c)
HEADERS = $(wildcard src/*.h)
CC = gcc
CFLAGS = -g -std=c99
LDFLAGS = -lm

default: simulator

simulator: $(SRCS) $(HEADERS)
@echo "Building $@..."
@#gcc simulator.o -o simulator -ggdb -std=c99
@echo "Sources: $(SRCS)"
@echo "Headers: $(HEADERS)"
$(CC) $(CFLAGS) -o $@ $(SRCS) $(LDFLAGS)

clean:
-rm -f assembled_tests/*
-rm -f simulator
-rm -f pipe_trace.txt *.out mdump.txt
26 changes: 26 additions & 0 deletions pa1/README.md
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# Programming Assignment 1: Non-pipelined riscy-uconn Simulator

A non-pipelined CPU simulator for the MIPS-like riscy-uconn instruction set architecture. The
simulator translates machine code created by the riscy-uconn assembler, and executes instructions
one at a time. Each instruction goes through a Fetch, Decode, Execute, Memory, and Writeback stage of
processing.

## Build Instructions
$ make

## Unit Tests
Several unit tests are provided in the `unittests` directory. These unit tests must be assembled
before use with the simulator. Ensure that the assembler is compiled (this should be done after completing PA0).
The unit tests can all be assembled by executing the following command:

$ ../assembler/assembler unittests/unit_test_file.asm unittests/unit_test_file.out

where `unit_test_file` is any of the unit test files (written in riscy-uconn assembly) in the
`unittests` directory. Note that you do not need to store the output files in the `unittests` directory.


## Usage
$ ./simulator assembled_tests/unit_test_file.out

where `unit_test_file.out` may be any assembled program file generated by the riscy-uconn
assembler.
40 changes: 40 additions & 0 deletions pa1/src/instruction_map.c
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/**
* University of Connecticut
* CSE 4302: Computer Architecture
* Fall 2022
*
* Programming Assignment 1: Non-pipelined Simulator
*
* riscy-uconn: instruction_map.c
*
* DO NOT MODIFY THIS FILE
*
*/

#include "instruction_map.h"

char* opcode_map[] = {
[RTYPEOP] = "RTYPEOP",
[LW] = "lw",
[SW] = "sw",
[ANDI] = "andi",
[ADDI] = "addi",
[ORI] = "ori",
[SLTI] = "slti",
[LUI] = "lui",
[BEQ] = "beq",
[BNE] = "bne",
[J] = "j",
[JAL] = "jal"
};

char* func_map[] = {
[ADD] = "add",
[SUB] = "sub",
[AND] = "and",
[OR] = "or",
[SLL] = "sll",
[SRL] = "srl",
[SLT] = "slt",
[JR] = "jr"
};
43 changes: 43 additions & 0 deletions pa1/src/instruction_map.h
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/**
* University of Connecticut
* CSE 4302: Computer Architecture
* Fall 2022
*
* Programming Assignment 1: Non-pipelined Simulator
*
* riscy-uconn: instruction_map.h
*
* DO NOT MODIFY THIS FILE
*
*/

#pragma once

extern char* opcode_map[];
extern char* func_map[];

/* R-Type Instructions */
#define RTYPEOP 0x0
#define ADD 0x20
#define SUB 0x21
#define AND 0x24
#define OR 0x25
#define SLL 0x0
#define SLT 0x2A
#define SRL 0x2
#define JR 0x8

/* I-Type Instructions */
#define LW 0x23
#define SW 0x2B
#define ANDI 0xC
#define ORI 0xD
#define LUI 0xF
#define BEQ 0x4
#define BNE 0x5
#define SLTI 0xA
#define ADDI 0x8

/* J-Type Instructions */
#define J 0x2
#define JAL 0x3
49 changes: 49 additions & 0 deletions pa1/src/register_map.c
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/**
* University of Connecticut
* CSE 4302: Computer Architecture
* Fall 2022
*
* Programming Assignment 1: Non-pipelined Simulator
*
* riscy-uconn: register_map.c
*
* DO NOT MODIFY THIS FILE
*
*/

#include "register_map.h"

const char* register_map[] = {
[0] = "zero",
[1] = "at",
[2] = "v0",
[3] = "v1",
[4] = "a0",
[5] = "a1",
[6] = "a2",
[7] = "a3",
[8] = "t0",
[9] = "t1",
[10] = "t2",
[11] = "t3",
[12] = "t4",
[13] = "t5",
[14] = "t6",
[15] = "t7",
[16] = "s0",
[17] = "s1",
[18] = "s2",
[19] = "s3",
[20] = "s4",
[21] = "s5",
[22] = "s6",
[23] = "s7",
[24] = "t8",
[25] = "t9",
[26] = "k0",
[27] = "k1",
[28] = "gp",
[29] = "sp",
[30] = "fp",
[31] = "ra",
};
13 changes: 13 additions & 0 deletions pa1/src/register_map.h
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#pragma once
/**
* University of Connecticut
* CSE 4302: Computer Architecture
* Fall 2022
*
* riscy-uconn: register_map.h
*
* DO NOT MODIFY THIS FILE
*
*/

extern const char* register_map[];
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