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README.md

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 # mipsivm
+The name of the project "mipsivm" is an abbreviation for "MIPS Interpreting Virtual Machine".
+
+## Introduction
+The "mipsivm" is a software-based Emulator project aiming to virtualize the minimum MIPS-based machine and efficient virtualized memory. <br>
+This project is an interpreting emulator project - providing the accurate emulation.
+
+## Processor Virtualization
+To virtualize the processor, we implement the VMCB structure. VMCB is the acronym that stands for Virtual Machine Control Block. A single VMCB will control a single vCPU. The VMCB would include the followings:
+- Memory Virtualization settings
+- Register File, including GPR and FPU
+- Execution Control, controlling the behavior of vCPU
+
+### Glossary of Processor Virtualization
+| Acronyms  | Abbreviated for               | Explanation                       |
+| --------- | ----------------------------- | --------------------------------- |
+| vCPU      | Virtual CPU                   | The virtual processor             |
+| FPU       | Floating Processing Unit      | Co-processor for floating number  |
+| RF        | Register File                 | Storage of Registers              |
+| GPR       | General Purpose Register      | Register of CPU                   |
+| VMCB      | Virtual Machine Control Block | Controlling Structure for a vCPU  |
+| MPT       | MIPS Page Table               | Address of Root of Paging         |
+
+## Memory Virtualization
+The memory virtualization is the special feature of the project. This project uses paging as inspired by AMD64 architecture. <br>
+The "mipsivm" will implement memory virtualization through paging. Memory access would be translated from GPA to HVA with constant running time complexity. <br>
+From AMD64 design, we may translate 32-bit address to 32-bit address through Non-PAE L2P; we may translate 32-bit address to 64-bit address through PAE L3P. Therefore, as a simulator running on Intel x86/AMD64, we have followings:
+
+### L2P Translation
+This option is for simulator being compiled as 32-bit code on Intel x86 platform. <br>
+The 32-bit GPA is divided into three parts:
+- 12-bit Offset: Offset to the page base.
+- 10-bit PTE: Index of page table. A single PTE controls 4KiB Memory.
+- 10-bit PDE: Index of page directory. A single PDE controls 4MiB Memory.
+
+It is also necessary for simulator to setup a page table. A page table starts with an address to the page-directory. The page directory should be 4KiB sized. <br>
+Each PDE is a 4-byte entry. Hence there are 1024 PDEs. For each entry, there are 32 bits. The higher 20 bits indicates the HVA of PTE. The lower 12 bits indicates the property of PDE, including the access control (to be read-only, read-write, executable, no-access, etc.) <br>
+Each PTE is a 4-byte entry. The HVA of PTE should be 4KiB-aligned. For each entry, there are 32 bits. The higher 20 bits indicates the HVA of page base. The lower 12-bits indicates the property of PTE, including the access control.
+
+### L3P Translation
+This option is for simulator being compiled as 64-bit code on AMD64 platform. <br>
+The 32-bit GPA is divided into four parts:
+- 12-bit Offset: Offset to the page base.
+- 9-bit PTE: Index of page table. A single PTE controls 4KiB Memory.
+- 9-bit PDE: Index of page directory. A single PDE controls 2MiB Memory.
+- 2-bit PDPTE: Index of page directory pointer table. A single PDPTE controls 1GiB Memory.
+
+The page table starts with an address to the page directory pointer table. It should be 32-byte sized.
+Each PDPTE is an 8-byte entry. There are 4 PDPTEs. For each entry, there are 64 bits. The higher 52 bits indicates the HVA of PDE. The lower 12 bits indicates the property of PDPTE, including the access control.
+Each PDE is an 8-byte entry. There are 512 PDEs. For each entry, there are 64 bits. The higher 52 bits indicates the HVA of PTE. The lower 12 bits indicates the property of PDE, including the access control.
+Each PTE is an 8-byte entry. There are 512 PTEs. For each entry, there are 64 bits. The higher 52 bits indicates the HVA of page base. The lower 12 bits indicates the property of PTE, including the access control.
+
+### Glossary of Memory Virtualization
+The glossary will be listed as a markdown list as followings
+| Acronyms  | Abbreviated for                       | Explanation                                       |
+| --------- | ------------------------------------- | ------------------------------------------------- |
+| GPA       | Guest Physical Address                | Address that referenced in simulated MIPS VM      |
+| HVA       | Host Virtual Address                  | Address that the Simulator would reference        |
+| L2P       | 2-Level Paging                        | 32-bit GPA to 32-bit HVA translation mechanism    |
+| L3P       | 3-Level Paging                        | 32-bit GPA to 64-bit HVA translation mechanism    |
+| PTE       | Page-Table Entry                      | The first level of address-translation            |
+| PDE       | Page-Directory Entry                  | The second level of address-translation           |
+| PDPTE     | Page-Directory Pointer Table Entry    | The third level of address-translation            |
+
+## FAQ
+Following lists the frequently asked questions, and corresponding answers.
+
+### Why the Project?
+In my sophomore year, I took the CSE3666 course - Introduction to Computer Architecture. In the final month of the semester, there is an emulator project - emulate an MIPS machine. The emulator skeleton is in either python or java implemention. I considered the implementation is not quite efficient. So this project is given birth by me - implement the emulator in an efficient interpreting method.
+
+### Is there a well-known open-source MIPS emulator project?
+Yes, there is. The famous PCSX2 is a free and open-source PlayStation 2 (PS2) emulator project. The processor inside the PS2 is based on MIPS Architecture.
+
+### What big difference does this project make?
+- It is the access-controlled memory-virtualization feature.
+- This project is written in C programming language.
+- This software is implemented by inspirations from AMD64 architecture.
+- This project aims to support more instructions.
+- This project uses most techniques on optimizations.
+
+## License
+This repository is licensed under the MIT license.