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SRCS = $(wildcard src/*.c) | ||
HEADERS = $(wildcard src/*.h) | ||
CC = gcc | ||
CFLAGS = -g -std=c99 | ||
LDFLAGS = -lm | ||
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default: simulator | ||
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simulator: $(SRCS) $(HEADERS) | ||
@echo "Building $@..." | ||
@echo "Sources: $(SRCS)" | ||
@echo "Headers: $(HEADERS)" | ||
$(CC) $(CFLAGS) -o $@ $(SRCS) $(LDFLAGS) | ||
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clean: | ||
-rm -f simulator | ||
-rm -f pipe_trace.txt *.out mdump.txt cdump.txt |
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# Programming Assignment 3: Pipelined riscy-uconn Simulator with Multi-cycle Operations and Data Cache | ||
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A 5-stage pipelined CPU simulator with multi-cycle operations and data cache for the MIPS-like | ||
riscy-uconn instruction set architecture. The simulator translates machine code created by the | ||
riscy-uconn assembler, and executes instructions one at a time. Each instruction goes through a | ||
Fetch, Decode, Execute, Memory and Writeback stage of processing. | ||
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## Build Instructions | ||
$ make | ||
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## Usage | ||
$ ./simulator assembled_program_file.out FORWARDING_ENABLED DATA_CACHE_ENABLED | ||
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where `assembled_program_file.out` may be any assembled program file generated by the riscy-uconn | ||
assembler, `FORWARDING_ENABLED` may be 0 (disabled) or 1 (enabled), and `DATA_CACHE_ENABLED` may be | ||
0 (disabled) or 1 (enabled). | ||
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## Unit Tests | ||
Several unit tests are provided in the `unittests` directory. These unit tests must be assembled | ||
before use with the simulator by executing the following command: | ||
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$ ../assembler/assembler unittests/unit_test_file.asm unittests/unit_test_file.out | ||
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where `unit_test_file` is any of the unit test files (written in riscy-uconn assembly) in the | ||
`unittests` directory. | ||
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/** | ||
* University of Connecticut | ||
* CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture | ||
* Fall 2021 | ||
* | ||
* Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache | ||
* | ||
* riscy-uconn: instruction_map.c | ||
* | ||
* DO NOT MODIFY THIS FILE | ||
* | ||
*/ | ||
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#include "instruction_map.h" | ||
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char* opcode_map[] = { | ||
[RTYPEOP] = "RTYPEOP", | ||
[LW] = "lw", | ||
[SW] = "sw", | ||
[ANDI] = "andi", | ||
[ADDI] = "addi", | ||
[ORI] = "ori", | ||
[SLTI] = "slti", | ||
[LUI] = "lui", | ||
[BEQ] = "beq", | ||
[BNE] = "bne", | ||
[J] = "j", | ||
[JAL] = "jal" | ||
}; | ||
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char* func_map[] = { | ||
[ADD] = "add", | ||
[SUB] = "sub", | ||
[AND] = "and", | ||
[OR] = "or", | ||
[SLL] = "sll", | ||
[SRL] = "srl", | ||
[SLT] = "slt", | ||
[JR] = "jr" | ||
}; |
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/** | ||
* University of Connecticut | ||
* CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture | ||
* Fall 2021 | ||
* | ||
* Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache | ||
* | ||
* riscy-uconn: instruction_map.h | ||
* | ||
* DO NOT MODIFY THIS FILE | ||
* | ||
*/ | ||
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#pragma once | ||
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extern char* opcode_map[]; | ||
extern char* func_map[]; | ||
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/* R-Type Instructions */ | ||
#define RTYPEOP 0x0 | ||
#define ADD 0x20 | ||
#define SUB 0x21 | ||
#define AND 0x24 | ||
#define OR 0x25 | ||
#define SLL 0x0 | ||
#define SLT 0x2A | ||
#define SRL 0x2 | ||
#define JR 0x8 | ||
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/* I-Type Instructions */ | ||
#define LW 0x23 | ||
#define SW 0x2B | ||
#define ANDI 0xC | ||
#define ORI 0xD | ||
#define LUI 0xF | ||
#define BEQ 0x4 | ||
#define BNE 0x5 | ||
#define SLTI 0xA | ||
#define ADDI 0x8 | ||
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/* J-Type Instructions */ | ||
#define J 0x2 | ||
#define JAL 0x3 |
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/** | ||
* University of Connecticut | ||
* CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture | ||
* Fall 2021 | ||
* | ||
* Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache | ||
* | ||
* riscy-uconn: register_map.c | ||
* | ||
* DO NOT MODIFY THIS FILE | ||
* | ||
*/ | ||
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#include "register_map.h" | ||
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const char* register_map[] = { | ||
[0] = "zero", | ||
[1] = "at", | ||
[2] = "v0", | ||
[3] = "v1", | ||
[4] = "a0", | ||
[5] = "a1", | ||
[6] = "a2", | ||
[7] = "a3", | ||
[8] = "t0", | ||
[9] = "t1", | ||
[10] = "t2", | ||
[11] = "t3", | ||
[12] = "t4", | ||
[13] = "t5", | ||
[14] = "t6", | ||
[15] = "t7", | ||
[16] = "s0", | ||
[17] = "s1", | ||
[18] = "s2", | ||
[19] = "s3", | ||
[20] = "s4", | ||
[21] = "s5", | ||
[22] = "s6", | ||
[23] = "s7", | ||
[24] = "t8", | ||
[25] = "t9", | ||
[26] = "k0", | ||
[27] = "k1", | ||
[28] = "gp", | ||
[29] = "sp", | ||
[30] = "fp", | ||
[31] = "ra", | ||
}; |
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/** | ||
* University of Connecticut | ||
* CSE 4302 / CSE 5302 / ECE 5402: Computer Architecture | ||
* Fall 2021 | ||
* | ||
* Programming Assignment 3: Pipelined Simulator with Multi-cycle Operations and Data Cache | ||
* | ||
* riscy-uconn: register_map.h | ||
* | ||
* DO NOT MODIFY THIS FILE | ||
* | ||
*/ | ||
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#pragma once | ||
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extern const char* register_map[]; |
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