.

assembler/README.md

@@ -1,10 +1,10 @@
-Mips Assembler
+RISC-V Assembler
 ==============
 
-An assembler for a subset of the MIPS like instruction set architecture
+An assembler for a subset of the RISC-V like instruction set architecture
 
 # How to use
-The assembler will take a file written in assembly language as input on the command line and will produce an output file containing the MIPS machine code. The input file should be in ASCII text. Each line in the input assembly file contains either a mnemonic, a section header (such as .data) or a label (jump or branch target. The maximum length of a line is 4 bytes. Section headers such as .data and .text should be in a line by themselves with no other assembly mnemonic. Similarly, branch targets such as loop: will be on a line by themselves with no other assembly mnemonic. The input assembly file should only contain one data section and one text section. The first section in the file will be the .text section, followed by the .data section.
+The assembler will take a file written in assembly language as input on the command line and will produce an output file containing the RISC-V machine code. The input file should be in ASCII text. Each line in the input assembly file contains either a mnemonic, a section header (such as .data) or a label (jump or branch target). The maximum length of a line is 4 bytes. Section headers such as .data and .text should be in a line by themselves with no other assembly mnemonic. Similarly, branch targets such as loop: will be on a line by themselves with no other assembly mnemonic. The input assembly file should only contain one data section and one text section. The first section in the file will be the .text section, followed by the .data section.
 
 The assembler supports the following instruction set:
 
@@ -13,29 +13,40 @@ R-Type
 - sub
 - and
 - or
-- sll
+- xor
 - slt
+- sll
 - srl
-- jr
 
 I-Type
 - lw
-- sw
-- andi
+- jalr
 - addi
-- slti
+- andi
 - ori
-- lui
+- xori
+- slti
+- slli
+- srli
+
+S-Type
+- sw
+
+B-Type
 - beq
 - bne
+- blt
+- bge
+
+U-Type
+- lui
 
 J-Type
-- j
 - jal
 
 # Run
     to compile the assembler
     $ ./make
 
     to run the assembler on a nop.asm assembly file to write machine code in nop.out
-    $ ./assembler nop.asm nop.out
+    $ ./assembler nop.asm nop.out

pa1/README.md

@@ -1,4 +1,4 @@
-# Programming Assignment 1: Non-pipelined riscy-uconn Simulator
+# Programming Assignment 1: Non-pipelined riscv-uconn Simulator
 
 A non-pipelined CPU simulator for the RISC-V riscv-uconn instruction set architecture. The
 simulator translates machine code created by the riscv-uconn assembler, and executes instructions
@@ -13,15 +13,15 @@ Several unit tests are provided in the `unittests` directory. These unit tests m
 before use with the simulator. Ensure that the assembler is compiled (this should be done after completing PA0). 
 The unit tests can all be assembled by executing the following command:
 
-    $ ../assembler/assembler unittests/unit_test_file.asm unittests/unit_test_file.out
+    $ ../assembler/assembler unittests/unit_test_file.asm <path>/unit_test_file.out
 
-where `unit_test_file` is any of the unit test files (written in riscy-uconn assembly) in the
-`unittests` directory. Note that you do not need to store the output files in the `unittests` directory. You may also use the provided `assemble_all.sh' script:
+where `unit_test_file` is any of the unit test files (written in riscv-uconn assembly) in the
+`unittests` directory. You may also use the provided `assemble_all.sh' script:
 
     $ bash assemble_all.sh
 
 ## Usage
-    $ ./simulator unittests/unit_test_file.out
+    $ ./simulator <path>/unit_test_file.out
 
-where `unit_test_file.out` may be any assembled program file generated by the riscy-uconn
-assembler.
+where `unit_test_file.out` may be any assembled program file generated by the riscv-uconn
+assembler.

pa1/src/instruction_map.h

@@ -11,7 +11,6 @@
  * 
  */
 
-
 #pragma once
 
 /* Some helpful defines for decoding instructions */
@@ -33,30 +32,29 @@
 /* Opcode Bits */
 #define RTYPE        0x33
 #define ITYPE_ARITH  0x13
-#define ITYPE_LOAD   0x3
+#define ITYPE_LOAD   0x03
 #define STYPE        0x23
 #define BTYPE        0x63
 #define LUI          0x37
 #define JAL          0x6F
 #define JALR         0x67
 
 /* Funct3 Bits */
-/* R and I-Type Arithmetic */
+/* R-Type and I-Type Arithmetic */
 #define ADD_SUB      0b000
-#define SUB          0b000
 #define SLT          0b010
 #define SLL          0b001
 #define SRL          0b101
 #define AND          0b111
 #define OR           0b110
 #define XOR          0b100
-/* I-type JALR and Load, S-type, and B-type */
+/* I-type Load, S-type Store, and B-type */
 #define LW_SW        0b010
 #define BEQ          0b000
 #define BNE          0b001
 #define BLT          0b100
 #define BGE          0b101
 
 /* R-type Funct7s */
-#define ADD_F7       0x0
+#define ADD_F7       0x00
 #define SUB_F7       0x20

pa1/src/sim_stages.c

@@ -51,7 +51,7 @@ struct State fetch(void) {
 struct State decode(struct State fetch_out) {
 
     /**
-     * TODO: Decode the 32-bit instruction (fetch_out.inst). Populate the fetch_out structure as necessary.
+     * TODO: Your code for the decode stage here.
     */
 
     return fetch_out;